Datasheet AD9683 (Analog Devices) - 22

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Data Sheet AD9683 CLOCK INPUT CONSIDERATIONS Mini-Circuits®
The AD9683 has two options for deriving the input sampling clock:
ADT1-1WT, 1:1Z ADC
a differential Nyquist sampling clock input or an RF clock input
390pF 390pF CLOCK XFMR CLK+
(which is internally divided by 2 or 4). The clock input is selected in
INPUT 50Ω 100Ω
Address 0x09 and by default is configured for the Nyquist clock
390pF CLK–
input. For optimum performance, clock the AD9683 Nyquist
SCHOTTKY
049
DIODES:
sample clock input, CLK+ and CLK−, with a differential signal.
HSMS2822
1410- 1 The signal is typically ac-coupled into the CLK+ and CLK− pins Figure 49. Transformer-Coupled Differential Clock (Up to 200 MHz) via a transformer or via capacitors. These pins are biased internal y (see Figure 48) and require no external bias. If the clock inputs are floated, CLK− is pulled slightly lower than CLK+ to prevent
25Ω ADC
spurious clocking.
390pF 390pF CLOCK INPUT CLK+ Nyquist Clock Input Options 390pF
The AD9683 Nyquist clock input supports a differential clock
1nF CLK–
between 40 MHz and 625 MHz. The clock input structure supports
25Ω SCHOTTKY
050
DIODES:
differential input voltages from 0.3 V to 3.6 V and is therefore
HSMS2822
1410- 1 compatible with various logic family inputs such as CMOS, Figure 50. Balun-Coupled Differential Clock (Up to 625 MHz) LVDS, and LVPECL. A sine wave input is also accepted, but In some cases, it is desirable to buffer or generate multiple higher slew rates typically provide optimal performance. Clock clocks from a single source. In those cases, Analog Devices, Inc., source jitter is a critical parameter that can affect performance, as offers clock drivers with excellent jitter performance. Figure 51 described in the Jitter Considerations section. If the inputs are shows a typical PECL driver circuit that uses PECL drivers such floated, pul the CLK− pin low to prevent spurious clocking. as the AD9510, AD9511, AD9512, AD9513, AD9514, AD9515, The Nyquist clock input pins, CLK+ and CLK−, are internally AD9516-0 through AD9516-5 device family, AD9517-0 through biased to 0.9 V and have a typical input impedance of 4 pF in AD9517-4 device family, AD9518-0 through AD9518-4 device parallel with 10 kΩ (see Figure 48). The input clock is typically family, AD9520-0 through AD9520-5 device family, AD9522-0 ac-coupled to CLK+ and CLK−. Figure 49 through Figure 52 through AD9522-5 device family, AD9523, AD9524, and present some typical clock drive circuits for reference. ADCLK905/ADCLK907/ADCLK925.
AVDD 0.1µF 0.1µF ADC CLOCK CLK+ 0.9V INPUT AD95xx 100Ω CLK+ CLK– PECL DRIVER 0.1µF 0.1µF CLOCK CLK– INPUT 4pF 4pF 50k 240 Ω 50kΩ Ω 240Ω
051 1410- 1 048 Figure 51. Differential PECL Sample Clock (Up to 625 MHz) 1410- 1 Figure 48. Equivalent Nyquist Clock Input Circuit Analog Devices also offers LVDS clock drivers with excel ent jitter For applications where a single-ended low jitter clock between performance. A typical circuit is shown in Figure 52. It uses 40 MHz and 200 MHz is available, an RF transformer is LVDS drivers such as the AD9510, AD9511, AD9512, AD9513, recommended. Figure 49 shows an example using an RF AD9514, AD9515, AD9516-0 through AD9516-5 device family, transformer in the clock network. At frequencies above 200 MHz, AD9517-0 through AD9517-4 device family, AD9518-0 through an RF balun is recommended, as seen in Figure 50. The back-to- AD9518-4 device family, AD9520-0 through AD9520-5 device back Schottky diodes across the transformer secondary limit family, AD9522-0 through AD9522-5 device family, AD9523, clock excursions into the AD9683 to approximately 0.8 V p-p and AD9524. differential. This limit helps prevent the large voltage swings of the clock from feeding through to other portions of the AD9683,
0.1µF 0.1µF ADC
yet preserves the fast rise and fall times of the clock, which are
CLOCK CLK+ INPUT
critical to low jitter performance.
AD95xx 100Ω 0.1µF LVDS DRIVER 0.1µF CLOCK CLK– INPUT 50kΩ 50kΩ
052 1410- 1 Figure 52. Differential LVDS Sample Clock (Up to 625 MHz) Rev. D | Page 21 of 44 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY PRODUCT HIGHLIGHTS SPECIFICATIONS ADC DC SPECIFICATIONS ADC AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Input Common Mode Differential Input Configurations VOLTAGE REFERENCE CLOCK INPUT CONSIDERATIONS Nyquist Clock Input Options RF Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations POWER DISSIPATION AND STANDBY MODE DIGITAL OUTPUTS JESD204B TRANSMIT TOP LEVEL DESCRIPTION JESD204B Overview JESD204B Synchronization Details CGS Phase ILAS Phase Data Transmission Phase Link Setup Parameters Disable Lane Before Changing Configuration Configure Detailed Options Check FCHK, Checksum of JESD204B Interface Parameters Set Additional Digital Output Configuration Options Reenable Lane After Configuration Frame and Lane Alignment Monitoring and Correction Digital Outputs and Timing ADC OVERRANGE AND GAIN CONTROL ADC Overrange (OR) Gain Switching Fast Threshold Detection (FD) DC CORRECTION (DCC) DC CORRECTION BANDWIDTH DC CORRECTION READBACK DC CORRECTION FREEZE DC CORRECTION ENABLE BITS SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open and Reserved Locations Default Values Logic Levels Transfer Register Map MEMORY MAP REGISTER TABLE MEMORY MAP REGISTER DESCRIPTIONS PDWN Modes (Address 0x08) Output Mode (Address 0x14) SYNCINB±/SYSREF± Control (Address 0x3A) DC Correction Control (Address 0x40) DC Correction Value 0 (Address 0x41) DC Correction Value 1 (Address 0x42) Fast Detect Control (Address 0x45) Fast Detect Upper Threshold (Address 0x47 and Address 0x48) Fast Detect Lower Threshold (Address 0x49 and Address 0x4A) Fast Detect Dwell Time (Address 0x4B and Address  0x4C) JESD204B Quick Configuration (Address 0x5E) JESD204B Link Control 1 (Address 0x5F) JESD204B Link Control 2 (Address 0x60) JESD204B Link Control 3 (Address 0x61) JESD204B Device Identification (DID) Configuration (Address 0x64) JESD204B Bank Identification (BID) Configuration (Address 0x65) JESD204B Lane Identification (LID) Configuration (Address 0x67) JESD204B Scrambler (SCR) and Lane (L) Configuration (Address 0x6E) JESD204B Parameter, F (Address 0x6F, Read Only) JESD204B Parameter, K (Address 0x70) JESD204B Parameter, M (Address 0x71) JESD204B Parameters, N/CS (Address 0x72) JESD204B Parameter, Subclass/N’ (Address 0x73) JESD204B Samples per Converter per Frame Cycle (S) (Address 0x74) JESD204B Parameters HD and CF (Address 0x75) JESD204B Reserved 1 (Address 0x76) JESD204B Reserved 2 (Address 0x77) JESD204B Checksum (Address 0x79) JESD204B Output Driver Control (Address 0x80) JESD204B LMFC Offset (Address 0x8B) JESD204B Preemphasis (Address 0xA8) APPLICATIONS INFORMATION DESIGN GUIDELINES Power and Ground Recommendations Exposed Pad Thermal Heat Slug Recommendations VCM SPI Port OUTLINE DIMENSIONS ORDERING GUIDE