Datasheet AD7175-8 (Analog Devices) Производитель Analog Devices Описание 24-Bit, 8-/16-Channel, 250 kSPS, Sigma-Delta ADC with True Rail-to-Rail Buffers Страниц / Страница 65 / 1 — 24-Bit, 8-/16-Channel, 250 kSPS, Sigma-. Delta ADC with True Rail-to-Rail … Формат / Размер файла PDF / 1.1 Мб Язык документа английский
24-Bit, 8-/16-Channel, 250 kSPS, Sigma-. Delta ADC with True Rail-to-Rail Buffers. Data Sheet. AD7175-8. FEATURES
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Микросхема Преобразователь AD, ANALOG DEVICES AD7175-8BCPZ-RL7 Analog to Digital Converter, Sigma-Delta, 24Bit, 250KSPS, Single, Dual (+/-), 5.5V, 2V, LFCSP
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Модельный ряд для этого даташита Текстовая версия документа 24-Bit, 8-/16-Channel, 250 kSPS, Sigma- Delta ADC with True Rail-to-Rail Buffers Data Sheet AD7175-8 FEATURES GENERAL DESCRIPTION Fast and flexible output rate: 5 SPS to 250 kSPS The AD7175-8 is a low noise, fast settling, multiplexed, 8-/16-Channel scan data rate of 50 kSPS/channel (20 µs settling) channel (fully/pseudo differential) Σ-Δ analog-to-digitalPerformance specifications converter (ADC) for low bandwidth inputs. It has a maximum17.2 noise free bits at 250 kSPS channel scan rate of 50 kSPS (20 µs) for fully settled data. The20.2 noise free bits at 2.5 kSPS output data rates range from 5 SPS to 250 kSPS.24 noise free bits at 20 SPS The AD7175-8 integrates key analog and digital signal condition-INL: ±1 ppm of FSR ing blocks to allow users to configure an individual setup for85 dB filter rejection of 50 Hz and 60 Hz with 50 ms settling each analog input channel in use. Each feature can be user selectedUser configurable input channels on a per channel basis. Integrated true rail-to-rail buffers on the8 fully differential channels or 16 single-ended channels analog inputs and external reference inputs provide easy to driveCrosspoint multiplexer high impedance inputs. The precision 2.5 V low drift (2 ppm/°C)On-chip 2.5 V reference (±2 ppm/°C drift) band gap internal reference (with output reference buffer) addsTrue rail-to-rail analog and reference input buffers embedded functionality to reduce external component count.Internal or external clock Power supply: AVDD1 − AVSS = 5 V, AVDD2 = IOVDD = 2 V to The digital filter allows simultaneous 50 Hz and 60 Hz rejection5 V (nominal) at a 27.27 SPS output data rate. The user can switch betweenSplit supply with AVDD1/AVSS at ±2.5 V different filter options according to the demands of each channelADC current: 8.4 mA in the application. The ADC automatical y switches throughTemperature range: −40°C to +105°C each selected channel. Further digital processing functions3- or 4-wire serial digital interface (Schmitt trigger on SCLK) include offset and gain calibration registers, configurable on aSerial port interface (SPI), QSPI, MICROWIRE, and DSP per channel basis.compatible The device operates with a 5 V AVDD1 − AVSS supply, or withAPPLICATIONS ±2.5 V AVDD1/AVSS, and 2 V to 5 V AVDD2 and IOVDD nominal supplies. The specified operating temperature range isProcess control: PLC/DCS modules −40°C to +105°C. The AD7175-8 is available in a 40-lead LFCSPTemperature and pressure measurement package.Medical and scientific multichannel instrumentation Chromatography FUNCTIONAL BLOCK DIAGRAM AVDD1 AVDD2 REGCAPA REF– REF+ REFOUT IOVDD REGCAPD CROSSPOINT BUFFERED 1.8V MULTIPLEXER 1.8V PRECISION LDO LDO REFERENCE REFERENCE AIN0/REF2– AVDD INPUT INT BUFFERS REF CS AIN1/REF2+ SCLK SERIAL DIN Σ-Δ ADC DIGITAL INTERFACE FILTER AND CONTROL DOUT/RDY SYNC AIN15 ERROR ANALOG INPUT AVSS BUFFERS AIN16 XTAL AND INTERNAL I/O AND EXTERNAL CLOCK OSCILLATOR MUX CONTROL AD7175-8 CIRCUITRY TEMPERATURE SENSOR 001 1- 1AVSS PDSW GPIO0 GPIO1 GPO2 GPO3 XTAL1 XTAL2/CLKIO DGND 129 Figure 1.Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING CHARACTERISTICS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS NOISE PERFORMANCE AND RESOLUTION GETTING STARTED POWER SUPPLIES DIGITAL COMMUNICATION Accessing the ADC Register Map AD7175-8 RESET CONFIGURATION OVERVIEW Channel Configuration Channel Registers ADC Setups Setup Configuration Registers Filter Configuration Registers Gain Registers Offset Registers ADC Mode and Interface Mode Configuration ADC Mode Register Interface Mode Register Understanding Configuration Flexibility CIRCUIT DESCRIPTION BUFFERED ANALOG INPUT CROSSPOINT MULTIPLEXER Fully Differential Inputs Single-Ended Inputs AD7175-8 REFERENCE External Reference Internal Reference BUFFERED REFERENCE INPUT CLOCK SOURCE Internal Oscillator External Crystal External Clock DIGITAL FILTERS SINC5 + SINC1 FILTER SINC3 FILTER SINGLE CYCLE SETTLING ENHANCED 50 HZ AND 60 HZ REJECTION FILTERS OPERATING MODES CONTINUOUS CONVERSION MODE CONTINUOUS READ MODE SINGLE CONVERSION MODE STANDBY AND POWER-DOWN MODES CALIBRATION DIGITAL INTERFACE CHECKSUM PROTECTION CRC CALCULATION Polynomial Example of a Polynomial CRC Calculation—24-Bit Word: 0x654321 (Eight Command Bits and 16-Bit Data) XOR Calculation Example of an XOR Calculation—24-Bit Word: 0x654321 (Eight Command Bits and 16-Bit Data) INTEGRATED FUNCTIONS GENERAL-PURPOSE I/O EXTERNAL MULTIPLEXER CONTROL DELAY 16-BIT/24-BIT CONVERSIONS DOUT_RESET SYNCHRONIZATION Normal Synchronization Alternate Synchronization ERROR FLAGS ADC_ERROR CRC_ERROR REG_ERROR Input/Output DATA_STAT IOSTRENGTH POWER-DOWN SWITCH INTERNAL TEMPERATURE SENSOR GROUNDING AND LAYOUT REGISTER SUMMARY REGISTER DETAILS COMMUNICATIONS REGISTER STATUS REGISTER ADC MODE REGISTER INTERFACE MODE REGISTER REGISTER CHECK DATA REGISTER GPIO CONFIGURATION REGISTER ID REGISTER CHANNEL REGISTER 0 CHANNEL REGISTER 1 TO CHANNEL REGISTER 15 SETUP CONFIGURATION REGISTER 0 SETUP CONFIGURATION REGISTER 1 TO SETUP CONFIGURATION REGISTER 7 FILTER CONFIGURATION REGISTER 0 FILTER CONFIGURATION REGISTER 1 TO FILTER CONFIGURATION REGISTER 7 OFFSET REGISTER 0 OFFSET REGISTER 1 TO OFFSET REGISTER 7 GAIN REGISTER 0 GAIN REGISTER 1 TO GAIN REGISTER 7 OUTLINE DIMENSIONS ORDERING GUIDE