Datasheet AD9645 (Analog Devices) - 8

link to page 34 link to page 35
Data Sheet AD9645 Timing Diagrams
Refer to the Memory Map Register Descriptions section and Table 20 for SPI register settings.
N – 1 VINx± N t N + 1 A tEH tEL CLK– CLK+ tCPD DCO– DDR DCO+ DCO– SDR DCO+ tFCO tFRAME FCO– FCO+ t t D0A– PD DATA BITWISE D12 D10 D08 D06 D04 D02 LSB 0 D12 D10 D08 D06 D04 D02 LSB 0 MODE D0A+ N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 16 N – 16 N – 16 N – 16 N – 16 N – 16 N – 16 N – 16 t D1A– LD MSB D11 D09 D07 D05 D03 D01 0 MSB D11 D09 D07 D05 D03 D01 0 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 16 N – 16 N – 16 N – 16 N – 16 N – 16 N – 16 N – 16 D1A+ FCO– FCO+ D0A– BYTEWISE D05 D04 D03 D02 D01 LSB 0 0 D05 D04 D03 D02 D01 LSB 0 0 MODE N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 16 N – 16 N – 16 N – 16 N – 16 N – 16 N – 16 N – 16 D0A+ D1A– MSB D12 D11 D10 D09 D08 D07 D06 MSB D12 D11 D10 D09 D08 D07 D06
002
N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 16 N – 16 N – 16 N – 16 N – 16 N – 16 N – 16 N – 16 D1A+
10537- Figure 2. 16-Bit DDR/SDR, Two-Lane, 1× Frame Mode (Default)
N – 1 VINx± N + 1 tA N tEH tEL CLK– CLK+ DCO+ DDR DCO– DCO+ SDR DCO– tFRAME tFCO FCO– FCO+ t t PD DATA D0A– BITWISE D10 D08 D06 D04 D02 LSB D10 D08 D06 D04 D02 LSB MODE N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 16 N – 16 N – 16 N – 16 N – 16 N – 16 D0A+ t D1A– LD MSB D09 D07 D05 D03 D01 MSB D09 D07 D05 D03 D01 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 16 N – 16 N – 16 N – 16 N – 16 N – 16 D1A+ FCO– FCO+ D0A– BYTEWISE D05 D04 D03 D02 D01 LSB D05 D04 D03 D02 D01 LSB MODE N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 16 N – 16 N – 16 N – 16 N – 16 N – 16 D0A+ D1A– MSB D10 D09 D08 D07 D06 MSB D10 D09 D08 D07 D06
003
N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 16 N – 16 N – 16 N – 16 N – 16 N – 16 D1A+
10537- Figure 3. 12-Bit DDR/SDR, Two-Lane, 1× Frame Mode Rev. B | Page 7 of 36 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS AD9645-80 AD9645-125 EQUIVALENT CIRCUITS THEORY OF OPERATION ANALOG INPUT CONSIDERATIONS Input Common Mode Differential Input Configurations VOLTAGE REFERENCE CLOCK INPUT CONSIDERATIONS Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations POWER DISSIPATION AND POWER-DOWN MODE DIGITAL OUTPUTS AND TIMING SDIO/PDWN Pin SCLK/DFS Pin CSB Pin RBIAS Pin OUTPUT TEST MODES SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open Locations Default Values Logic Levels Channel-Specific Registers MEMORY MAP REGISTER TABLE MEMORY MAP REGISTER DESCRIPTIONS Device Index (Register 0x05) Transfer (Register 0xFF) Power Modes (Register 0x08) Bits[7:2]—Open Bits[1:0]—Power Mode Enhancement Control (Register 0x0C) Bits[7:3]—Open Bit 2—Chop Mode Bits[1:0]—Open Output Mode (Register 0x14) Bit 7—Open Bit 6—LVDS-ANSI/LVDS-IEEE Option Bits[5:3]—Open Bit 2—Output Invert Bit 1—Open Bit 0—Output Format Output Adjust (Register 0x15) Bits[7:6]—Open Bits[5:4]—Output Driver Termination Bits[3:1]—Open Bit 0—Output Drive Output Phase (Register 0x16) Bit 7—Open Bits[6:4]—Input Clock Phase Adjust Bits[3:0]—Output Clock Phase Adjust Serial Output Data Control (Register 0x21) Resolution/Sample Rate Override (Register 0x100) User I/O Control 2 (Register 0x101) Bits[7:1]—Open Bit 0—SDIO Pull-Down User I/O Control 3 (Register 0x102) Bits[7:4]—Open Bit 3—VCM Power-Down Bits[2:0]—Open APPLICATIONS INFORMATION DESIGN GUIDELINES POWER AND GROUND GUIDELINES CLOCK STABILITY CONSIDERATIONS EXPOSED PAD THERMAL HEAT SLUG RECOMMENDATIONS VCM REFERENCE DECOUPLING SPI PORT OUTLINE DIMENSIONS ORDERING GUIDE