Datasheet AD9635 (Analog Devices) - 3

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AD9635 Data Sheet TABLE OF CONTENTS
Features .. 1 Power Dissipation and Power-Down Mode ... 22 Applications ... 1 Digital Outputs and Timing ... 23 General Description ... 1 Output Test Modes ... 26 Functional Block Diagram .. 1 Serial Port Interface (SPI) .. 27 Product Highlights ... 1 Configuration Using the SPI ... 27 Revision History ... 2 Hardware Interface ... 28 Specifications ... 3 Configuration Without the SPI .. 28 DC Specifications ... 3 SPI Accessible Features .. 28 AC Specifications .. 4 Memory Map .. 29 Digital Specifications ... 5 Reading the Memory Map Register Table ... 29 Switching Specifications .. 6 Memory Map Register Table ... 30 Timing Specifications .. 6 Memory Map Register Descriptions .. 33 Absolute Maximum Ratings .. 10 Applications Information .. 35 Thermal Resistance .. 10 Design Guidelines .. 35 ESD Caution .. 10 Power and Ground Guidelines ... 35 Pin Configuration and Function Descriptions ... 11 Clock Stability Considerations ... 35 Typical Performance Characteristics ... 12 Exposed Pad Thermal Heat Slug Recommendations .. 35 AD9635-80 ... 12 VCM ... 35 AD9635-125 ... 15 Reference Decoupling .. 35 Equivalent Circuits ... 18 SPI Port .. 35 Theory of Operation .. 19 Outline Dimensions ... 36 Analog Input Considerations .. 19 Ordering Guide .. 36 Voltage Reference ... 20 Clock Input Considerations .. 21
REVISION HISTORY 10/15—Rev. A to Rev. B
Changes to Pin 21 Description ... 11 Changed tSAMPLE/16 to tSAMPLE/12, AD9516 to AD9516-0/ Changes to Voltage Reference Section ... 20 AD9516-1/AD9516-2/AD9516-3/AD9516-4/AD9516-5, Changes to Table 11 ... 25 and AD9517 to AD9517-0/AD9517-1/AD9517-2/AD9517-3/ Changes to First Paragraph of Serial Port Interface (SPI) AD9517-4 ... Throughout Section .. 27 Changes to General Description Section .. 1 Changes to SPI Accessible Features Section ... 28 Added Endnote 4, Table 4 ... 6 Changes to Output Phase (Register 0x16) Bits[6:4]—Input Changes to Digital Outputs and Timing Section ... 25 Clock Phase Adjust Section... 33 Changes to Resolution/Sample Rate Override (Register 0x100)
8/14—Rev. 0 to Rev. A
Section and User I/O Control 3 (Register 0x102) Bit 3—VCM Added Propagation Delay Parameters of 1.5 ns (min) Power-Down Section ... 34 and 3.1 ns (max), Table 4 ... 6 Added Clock Stability Considerations Section ... 35 Changes to Figure 2 and Figure 3 ... 7 Changes to Figure 4 and Figure 5 ... 8
6/12—Revision 0: Initial Version
Rev. B | Page 2 of 36 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS AD9635-80 AD9635-125 EQUIVALENT CIRCUITS THEORY OF OPERATION ANALOG INPUT CONSIDERATIONS Input Common Mode Differential Input Configurations VOLTAGE REFERENCE CLOCK INPUT CONSIDERATIONS Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations POWER DISSIPATION AND POWER-DOWN MODE DIGITAL OUTPUTS AND TIMING SDIO/PDWN Pin SCLK/DFS Pin CSB Pin RBIAS Pin OUTPUT TEST MODES SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open Locations Default Values Logic Levels Channel-Specific Registers MEMORY MAP REGISTER TABLE MEMORY MAP REGISTER DESCRIPTIONS Device Index (Register 0x05) Transfer (Register 0xFF) Power Modes (Register 0x08) Bits[7:2]—Open Bits[1:0]—Power Mode Enhancement Control (Register 0x0C) Bits[7:3]—Open Bit 2—Chop Mode Bits[1:0]—Open Output Mode (Register 0x14) Bit 7—Open Bit 6—LVDS-ANSI/LVDS-IEEE Option Bits[5:3]—Open Bit 2—Output Invert Bit 1—Open Bit 0—Output Format Output Adjust (Register 0x15) Bits[7:6]—Open Bits[5:4]—Output Driver Termination Bits[3:1]—Open Bit 0—Output Drive Output Phase (Register 0x16) Bit 7—Open Bits[6:4]—Input Clock Phase Adjust Bits[3:0]—Output Clock Phase Adjust Serial Output Data Control (Register 0x21) Resolution/Sample Rate Override (Register 0x100) User I/O Control 2 (Register 0x101) Bits[7:1]—Open Bit 0—SDIO Pull-Down User I/O Control 3 (Register 0x102) Bits[7:4]—Open Bit 3—VCM Power-Down Bits[2:0]—Open APPLICATIONS INFORMATION DESIGN GUIDELINES POWER AND GROUND GUIDELINES CLOCK STABILITY CONSIDERATIONS EXPOSED PAD THERMAL HEAT SLUG RECOMMENDATIONS VCM REFERENCE DECOUPLING SPI PORT OUTLINE DIMENSIONS ORDERING GUIDE