Datasheet AD9637 (Analog Devices) - 36

Data Sheet AD9637 Output Phase (Register 0x16) Resolution/Sample Rate Override (Register 0x100) Bit 7—Open
This register is designed to allow the user to downgrade the device.
Bits[6:4]—Input Clock Phase Adjust
Any attempt to upgrade the default speed grade results in a chip power-down. Settings in this register are not initialized until Bit 0 When the clock divider (Register 0x0B) is used, the applied of the transfer register (Register 0xFF) is written high. clock is at a higher frequency than the internal sampling clock. Bits[6:4] determine at which phase of the external
User I/O Control 2 (Register 0x101)
clock sampling occurs. This is only applicable when the
Bits[7:1]—Open
clock divider is used. Selecting Bits[6:4] greater than
Bit 0—SDIO Pull-Down
Register 0x0B Bits[2:0] is prohibited. Bit 0 can be set to disable the internal 30 kΩ pul -down on the
Table 19. Input Clock Phase Adjust Options
SDIO pin, which can be used to limit loading when many
Input Clock Phase Number of Input Clock Cycles of
devices are connected to the SPI bus.
Adjust, Bits[6:4] Phase Delay User I/O Control 3 (Register 0x102)
000 (Default) 0
Bits[7:4]—Open
001 1 010 2
Bit 3—VCM Power-Down
011 3 Bit 3 can be set high to power down the internal VCM generator. 100 4 This feature is used when applying an external reference. 101 5
Bits[2:0]—Open
110 6 111 7
Bits[3:0]—Output Clock Phase Adjust Table 20. Output Clock Phase Adjust Options Output Clock (DCO), DCO Phase Adjustment Phase Adjust, Bits[3:0] (Degrees Relative to D± x Edge)
0000 0 0001 60 0010 120 0011 (Default) 180 0100 240 0101 300 0110 360 0111 420 1000 480 1001 540 1010 600 1011 660 Rev. A | Page 35 of 40 Document Outline Features Applications General Description Functional Block Diagram Product Highlights Revision History Specifications DC Specifications AC Specifications Digital Specifications Switching Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings Thermal Characteristics ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics AD9637-80 AD9637-40 Equivalent Circuits Theory of Operation Analog Input Considerations Input Common Mode Differential Input Configurations Voltage Reference Internal Reference Connection External Reference Operation Clock Input Considerations Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations Power Dissipation and Power-Down Mode Digital Outputs and Timing SDIO/DFS Pin SCLK/DTP Pin CSB Pin RBIAS Pin Built-In Output Test Modes Output Test Modes Serial Port Interface (SPI) Configuration Using the SPI Hardware Interface Configuration Without the SPI SPI Accessible Features Memory Map Reading the Memory Map Register Table Open Locations Default Values Logic Levels Channel-Specific Registers Memory Map Register Table Memory Map Register Descriptions Device Index (Register 0x04 and Register 0x05) Transfer (Register 0xFF) Power Modes (Register 0x08) Bits[7:6]—Open Bits[1:0]—Internal Power-Down Mode Enhancement Control (Register 0x0C) Bits[7:3]—Open Bit 2—Chop Mode Bits[1:0]—Open Output Mode (Register 0x14) Bit 7—Open Bit 6—LVDS-ANSI/LVDS-IEEE Option Bits[5:3]—Open Bit 2—Output Invert Bit 1—Open Bit 0—Output Format Output Adjust (Register 0x15) Bits[7:6]—Open Bits[5:4]—Output Driver Termination Bits[3:1]—Open Bit 0—Output Drive Output Phase (Register 0x16) Bit 7—Open Bits[6:4]—Input Clock Phase Adjust Bits[3:0]—Output Clock Phase Adjust Resolution/Sample Rate Override (Register 0x100) User I/O Control 2 (Register 0x101) Bits[7:1]—Open Bit 0—SDIO Pull-Down User I/O Control 3 (Register 0x102) Bits[7:4]—Open Bit 3—VCM Power-Down Bits[2:0]—Open Applications Information Design Guidelines Power and Ground Recommendations Clock Stability Considerations Exposed Pad Thermal Heat Slug Recommendations VCM Reference Decoupling SPI Port Outline Dimensions Ordering Guide