Datasheet AD9608 (Analog Devices) - 10

Data Sheet AD9608 N – 1 N + 4 tA N + 5 N N + 3 VIN N + 1 N + 2 tCH tCLK CLK+ CLK– tDCO DCO– DCO+ tSKEW tPD D0+ (LSB) CH A CH B CH A CH B CH A CH B CH A CH B CH A N – 16 N – 16 N – 15 N – 15 N – 14 N – 14 N – 13 N – 13 N – 12 PARALLEL D0– (LSB) INTERLEAVED MODE D9+ (MSB) CH A CH B CH A CH B CH A CH B CH A CH B CH A D9– (MSB) N – 16 N – 16 N – 15 N – 15 N – 14 N – 14 N – 13 N – 13 N – 12 D1+/D0+ (LSB) CH A0 CH A1 CH A0 CH A1 CH A0 CH A1 CH A0 CH A1 CH A0 CHANNEL N – 16 N – 16 N – 15 N – 15 N – 14 N – 14 N – 13 N – 13 N – 12 MULTIPLEXED D1–/D0– (LSB) MODE D9+/D8+ (MSB) CHANNEL A CH A8 CH A9 CH A8 CH A9 CH A8 CH A9 CH A8 CH A9 CH A8 D9–/D8– (MSB) N – 16 N – 16 N – 15 N – 15 N – 14 N – 14 N – 13 N – 13 N – 12 D1+/D0+ (LSB) CH B0 CH B1 CH B0 CH B1 CH B0 CH B1 CH B0 CH B1 CH B0 CHANNEL N – 16 N – 16 N – 15 N – 15 N – 14 N – 14 N – 13 N – 13 N – 12 MULTIPLEXED D1–/D0– (LSB) MODE D9+/D8+ (MSB) CHANNEL B CH B8 CH B9 CH B8 CH B9 CH B8 CH B9 CH B8 CH B9 CH B8
004
D9–/D8– (MSB) N – 16 N – 16 N – 15 N – 15 N – 14 N – 14 N – 13 N – 13 N – 12
7- 0997 Figure 4. LVDS Modes for Data Output Timing
CLK+ t t SSYNC HSYNC
005
SYNC
977- 09 Figure 5. SYNC Input Timing Requirements Rev. C | Page 9 of 40 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS AD9608-125 AD9608-105 EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Input Common Mode Differential Input Configurations VOLTAGE REFERENCE Internal Reference Connection External Reference Operation CLOCK INPUT CONSIDERATIONS Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations CHANNEL/CHIP SYNCHRONIZATION POWER DISSIPATION AND STANDBY MODE DIGITAL OUTPUTS Digital Output Enable Function (OEB) TIMING Data Clock Output (DCO) OUTPUT TEST OUTPUT TEST MODES SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open Locations Default Values Logic Levels Channel-Specific Registers MEMORY MAP REGISTER TABLE MEMORY MAP REGISTER DESCRIPTIONS Power Modes (Register 0x08) Bits[7:6]—Open Bits[4:2]—Open Bits[1:0]—Internal Power-Down Mode Enhancement Control (Register 0x0C) Bits[7:3]—Open Bit 2—Chop Mode Bits[1:0]—Open Output Mode (Register 0x14) Bits[7:6]—Output Port Logic Type Bit 5—Output Interleave Enable Bit 4—Output Port Disable Bit 3—Open Bit 2—Output Invert Bits[1:0]—Output Format Sync Control (Register 0x3A) Bits[7:3]—Open Bit 2—Clock Divider Next Sync Only Bit 1—Clock Divider Sync Enable Bit 0—Open Transfer (Register 0xFF) Sample Rate Override (Register 0x100) User I/O Control 2 (Register 0x101) Bit 7—OEB Pin Enable Bits[6:1]—Open Bit 0—SDIO Pull-Down User I/O Control 3 (Register 0x102) Bits[7:4]—Open Bit 3—VCM Power-Down Bits[2:0]—Open APPLICATIONS INFORMATION DESIGN GUIDELINES Power and Ground Recommendations LVDS Operation Clock Stability Considerations Exposed Paddle Thermal Heat Slug Recommendations VCM Reference Decoupling SPI Port OUTLINE DIMENSIONS ORDERING GUIDE