Datasheet AD9643 (Analog Devices) - 2

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AD9643 Data Sheet TABLE OF CONTENTS
Features .. 1 Analog Input Considerations ... 23 Applications ... 1 Voltage Reference ... 25 Functional Block Diagram .. 1 Clock Input Considerations .. 25 General Description ... 1 Power Dissipation and Standby Mode .. 26 Product Highlights ... 1 Digital Outputs ... 27 Revision History ... 2 ADC Overrange (OR) .. 27 Specifications ... 3 Channel/Chip Synchronization .. 28 ADC DC Specifications ... 3 Serial Port Interface (SPI) .. 29 ADC AC Specifications ... 4 Configuration Using the SPI ... 29 Digital Specifications ... 6 Hardware Interface ... 29 Switching Specifications .. 8 SPI Accessible Features .. 30 Timing Specifications .. 9 Memory Map .. 31 Absolute Maximum Ratings .. 11 Reading the Memory Map Register Table ... 31 Thermal Characteristics .. 11 Memory Map Register Table ... 32 ESD Caution .. 11 Memory Map Register Description ... 34 Pin Configurations and Function Descriptions ... 12 Applications Information .. 35 Typical Performance Characteristics ... 16 Design Guidelines .. 35 Equivalent Circuits ... 22 Outline Dimensions ... 36 Theory of Operation .. 23 Ordering Guide .. 36 ADC Architecture .. 23
REVISION HISTORY 1/14—Rev. D to Rev. E 9/11—Rev. A to Rev. B
Changes to Figure 32 .. 29 Changes to Table 1 ... 3
2/13—Rev. C to Rev. D
Changes to Table 2, ... 4 Changes to Table 3 ... 6 Added tSSYNC and tHSYNC Minimum Parameters of 1 ns, Table 5 .. 9 Changes to Table 4 ... 8
1/13—Rev. B to Rev. C
Changes to Table 8 .. 12 Changes to Features Section.. 1 Changes to Table 9 .. 14 Changes to Input Referred Noise Parameter, Table 1 .. 3 Changes to Typical Performance Characterisitics Section ... 16 Changes to Table 2 .. 4 Added ADC Overrange (OR) Section ... 27 Change to Table 3 ... 6 Changes to Channel/Chip Synchronization Section ... 28 Changes to Table 4 .. 8 Changes to Reading the Memory Map Register Table Changes to Figure 5 .. 14 Section .. 31 Changes to Figure 29 .. 19 Changes to Table 14 ... 32 Changes to Figure 30 .. 20 Changes to Memory Map Resgister Description Section ... 34 Change to Reading the Memory Map Register Table Section ... 31
5/11—Rev. 0 to Rev. A
Changes to Table 14 .. 33 Changes to Table 2, Worst Other (Harmonic or Spur) Change to Memory Map Register Description Section... 34 Max Values ... 4 Updated Outline Dimensions ... 36
4/11—Revision 0: Initial Version
Rev. E | Page 2 of 36 Document Outline Features Applications Functional Block Diagram General Description Product Highlights Table of Contents Revision History Specifications ADC DC Specifications ADC AC Specifications Digital Specifications Switching Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings Thermal Characteristics ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Equivalent Circuits Theory of Operation ADC Architecture Analog Input Considerations Input Common Mode Differential Input Configurations Voltage Reference Clock Input Considerations Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations Power Dissipation and Standby Mode Digital Outputs Digital Output Enable Function (OEB) Timing Data Clock Output (DCO) ADC Overrange (OR) Channel/Chip Synchronization Serial Port Interface (SPI) Configuration Using the SPI Hardware Interface SPI Accessible Features Memory Map Reading the Memory Map Register Table Open and Reserved Locations Default Values Logic Levels Transfer Register Map Channel-Specific Registers Memory Map Register Table Memory Map Register Description Sync Control (Register 0x3A) Bits[7:3]—Reserved Bit 2—Clock Divider Next Sync Only Bit 1—Clock Divider Sync Enable Bit 0—Master Sync Buffer Enable Applications Information Design Guidelines Power and Ground Recommendations Exposed Paddle Thermal Heat Slug Recommendations VCM SPI Port Outline Dimensions Ordering Guide