Datasheet AD9613 (Analog Devices) - 27

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Data Sheet AD9613 1000pF 180nH 220nH 1µH VPOS 165Ω 15pF AD9613 AD8376 301Ω 5.1pF 3.9pF VCM 165Ω 2.5kΩ║2pF 1µH 1nF 1nF 68nH 1000pF 180nH 220nH NOTES 1. ALL INDUCTORS ARE COILCRAFT 0603CS COMPONENTS WITH THE EXCEPTION OF THE 1µH CHOKE INDUCTORS (0603LS).
54 0
2. FILTER VALUES SHOWN FOR A 20MHz BANDWIDTH FILTER
7-
CENTERED AT 140MHz.
963 0 Figure 50. Differential Input Configuration Using the AD8376 (Filter Values Shown for a 20 MHz Bandwidth Filter Centered at 140 MHz)
VOLTAGE REFERENCE
the clock from feeding through to other portions of the AD9613, A stable and accurate voltage reference is built into the while preserving the fast rise and fall times of the signal, which are AD9613. The full-scale input range can be adjusted by varying the critical to low jitter performance. reference voltage via SPI. The input span of the ADC tracks
Mini-Circuits®
reference voltage changes linearly.
ADT1-1WT, 1:1Z ADC 390pF 390pF CLOCK INPUT CONSIDERATIONS CLOCK XFMR CLK+ INPUT 50Ω 100Ω
For optimum performance, the AD9613 sample clock inputs,
390pF
CLK+ and CLK−, should be clocked with a differential signal. The
CLK–
056
SCHOTTKY
637- signal is typically ac-coupled into the CLK+ and CLK− pins via
DIODES: HSMS2822
09 a transformer or via capacitors. These pins are biased internally Figure 52. Transformer Coupled Differential Clock (Up to 200 MHz) (see Figure 51) and require no external bias. If the inputs are floated, the CLK− pin is pulled low to prevent spurious clocking.
25Ω ADC AVDD 390pF 390pF CLOCK INPUT CLK+ 390pF 0.9V CLK– 25Ω SCHOTTKY
57 0
CLK+ CLK– DIODES:
7-
HSMS2822
963 0
4pF 4pF
Figure 53. Balun-Coupled Differential Clock (Up to 625 MHz) 55 If a low jitter clock source is not available, another option is to 0 37- 96 ac-couple a differential PECL signal to the sample clock input 0 Figure 51. Simplified Equivalent Clock Input Circuit pins, as shown in Figure 54. The AD9510, AD9511, AD9512,
Clock Input Options
AD9513, AD9514, AD9515, AD9516, AD9517, AD9518, AD9520, AD9522, AD9523, AD9524, and ADCLK905/ADCLK907/ The AD9613 has a very flexible clock input structure. Clock ADCLK925 clock drivers offer excellent jitter performance. input can be a CMOS, LVDS, LVPECL, or sine wave signal. Regardless of the type of signal being used, clock source jitter is of the most concern, as described in the Jitter Considerations
0.1µF 0.1µF ADC
section.
CLOCK CLK+ INPUT
Figure 52 and Figure 53 show two preferable methods for
AD95xx 100Ω 0.1µF PECL DRIVER
clocking the AD9613 (at clock rates of up to 625 MHz). A low
0.1µF CLOCK CLK–
jitter clock source is converted from a single-ended signal to a
INPUT 50kΩ 50kΩ 240Ω 240Ω
058 7- differential signal using an RF balun or RF transformer. 0963 The RF balun configuration is recommended for clock frequencies Figure 54. Differential PECL Sample Clock (Up to 625 MHz) between 125 MHz and 625 MHz, and the RF transformer is recommended for clock frequencies from 10 MHz to 200 MHz. The back-to-back Schottky diodes across the transformer secondary limit clock excursions into the AD9613 to approximately 0.8 V p-p differential. This limit helps prevent the large voltage swings of Rev. D | Page 25 of 36 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS REVISION HISTORY SPECIFICATIONS ADC DC SPECIFICATIONS ADC AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Input Common Mode Differential Input Configurations VOLTAGE REFERENCE CLOCK INPUT CONSIDERATIONS Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations POWER DISSIPATION AND STANDBY MODE DIGITAL OUTPUTS Digital Output Enable Function (OEB) Timing Data Clock Output (DCO) ADC OVERRANGE (OR) CHANNEL/CHIP SYNCHRONIZATION SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open and Reserved Locations Default Values Logic Levels Transfer Register Map Channel Specific Registers MEMORY MAP REGISTER TABLE MEMORY MAP REGISTER DESCRIPTION Sync Control (Register 0x3A) Bits[7:3]—Reserved Bit 2—Clock Divider Next Sync Only Bit 1—Clock Divider Sync Enable Bit 0—Master Sync Buffer Enable APPLICATIONS INFORMATION DESIGN GUIDELINES Power and Ground Recommendations Exposed Paddle Thermal Heat Slug Recommendations VCM SPI Port OUTLINE DIMENSIONS ORDERING GUIDE