Datasheet AD9484 (Analog Devices) - 3

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AD9484 TABLE OF CONTENTS
Features .. 1  Theory of Operation .. 14  Applications ... 1  Analog Input and Voltage Reference ... 14  Functional Block Diagram .. 1  Clock Input Considerations .. 15  General Description ... 1  Power Dissipation and Power-Down Mode ... 16  Product Highlights ... 1  Digital Outputs ... 16  Revision History ... 2  Timing ... 17  Specifications ... 3  VREF .. 17  DC Specifications ... 3  AD9484 Configuration Using the SPI ... 18  AC Specifications .. 4  Hardware Interface ... 18  Digital Specifications ... 5  Configuration Without the SPI .. 18  Switching Specifications .. 6  Memory Map .. 20  Absolute Maximum Ratings .. 7  Reading the Memory Map Table .. 20  Thermal Resistance .. 7  Reserved Locations .. 20  ESD Caution .. 7  Default Values ... 20  Pin Configuration and Function Descriptions ... 8  Logic Levels ... 20  Typical Performance Characteristics ... 10  Outline Dimensions ... 23  Equivalent Circuits ... 13  Ordering Guide .. 23 
REVISION HISTORY 6/11—Rev. 0 to Rev. A
Change to General Description Section .. 1 Change to Aperture Time Parameter in Table 4 ... 6 Change to Figure 34 ... 16 Changes to Register 17 and Register 18 in Table 12 .. 20
3/11—Revision 0: Initial Version
Rev. A | Page 2 of 24 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS Timing Diagram ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS THEORY OF OPERATION ANALOG INPUT AND VOLTAGE REFERENCE Differential Input Configurations CLOCK INPUT CONSIDERATIONS Clock Duty Cycle Considerations Clock Jitter Considerations POWER DISSIPATION AND POWER-DOWN MODE DIGITAL OUTPUTS Digital Outputs and Timing Output Data Rate and Pinout Configuration Out-of-Range (OR) TIMING VREF AD9484 CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI MEMORY MAP READING THE MEMORY MAP TABLE RESERVED LOCATIONS DEFAULT VALUES LOGIC LEVELS OUTLINE DIMENSIONS ORDERING GUIDE