Datasheet AD9434 (Analog Devices) - 8

Data Sheet AD9434 Timing Diagrams N – 1 t N + 4 A N + 5 N N + 3 VIN+, VIN– N + 1 N + 2 tCH tCL 1/fS CLK+ CLK– tCPD DCO+ DCO– tSKEW tPD Dx+ N – 15 N – 14 N – 13 N – 12 N – 11 Dx–
-002 383 09 Figure 2. Single Data Rate Mode
N – 1 t N + 4 A N + 5 N N + 3 VIN+, VIN– N + 1 N + 2 tCH tCL 1/fS CLK+ CLK– tCPD DCO+ DCO– tSKEW tPD D0/D6+ D6 D0 D6 D0 D6 D0 D6 D0 D6 D0 N – 15 N – 14 N – 14 N – 13 N – 13 N – 12 N – 12 N – 11 N – 11 N – 10 D0/D6– D5/D11+ D11 D5 D11 D5 D11 D5 D11 D5 D11 D5 N – 15 N – 14 N – 14 N – 13 N – 13 N – 12 N – 12 N – 11 N – 11 N – 10 D5/D11– 6 MSBs
03 0
6 LSBs
9383- 0 Figure 3. Double Data Rate Mode Rev. B | Page 7 of 28 Document Outline Features Applications General Description Functional Block Diagram Product Highlights Revision History Specifications DC Specifications AC Specifications Digital Specifications Switching Specifications Timing Diagrams Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Equivalent Circuits Theory of Operation Analog Input and Voltage Reference Differential Input Configurations Clock Input Considerations Clock Duty Cycle Considerations Clock Jitter Considerations Power Dissipation and Power-Down Mode Digital Outputs Digital Outputs and Timing Output Data Rate and Pinout Configuration Out-of-Range (OR) Timing VREF AD9434 Configuration Using the SPI Using the AD9434 to Replace the AD9230 Hardware Interface Configuration Without the SPI Memory Map Reading the Memory Map Table Reserved Locations Default Values Logic Levels Outline Dimensions Ordering Guide