Datasheet AD7606, AD7606-6, AD7606-4 (Analog Devices) - 32

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AD7606/AD7606-6/AD7606-4 Data Sheet LAYOUT GUIDELINES
Figure 62 shows the recommended decoupling on the top layer The printed circuit board that houses the AD7606/AD7606-6/ of the AD7606 board. Figure 63 shows bottom layer decoupling, AD7606-4 should be designed so that the analog and digital which is used for the four AVCC pins and the VDRIVE pin decoupling. sections are separated and confined to different areas of the board. Where the ceramic 100 nF caps for the AVCC pins are placed close to their respective device pins, a single 100 nF capacitor At least one ground plane should be used. It can be common or can be shared between Pin 37 and Pin 38. split between the digital and analog sections. In the case of the split plane, the digital and analog ground planes should be joined in only one place, preferably as close as possible to the AD7606/AD7606-6/AD7606-4. If the AD7606/AD7606-6/AD7606-4 are in a system where multiple devices require analog-to-digital ground connections, the connection should stil be made at only one point: a star ground point that should be established as close as possible to the AD7606/AD7606-6/AD7606-4. Good connections should be made to the ground plane. Avoid sharing one connection for multiple ground pins. Use individual vias or multiple vias to the ground plane for each ground pin. Avoid running digital lines under the devices because doing so couples noise onto the die. The analog ground plane should be 054 al owed to run under the AD7606/AD7606-6/AD7606-4 to 08479- avoid noise coupling. Fast switching signals like CONVST A, Figure 62. Top Layer Decoupling REFIN/REFOUT, CONVST B, or clocks should be shielded with digital ground REFCAPA, REFCAPB, and REGCAP Pins to avoid radiating noise to other sections of the board, and they should never run near analog signal paths. Avoid crossover of digital and analog signals. Traces on layers in close proximity on the board should run at right angles to each other to reduce the effect of feedthrough through the board. The power supply lines to the AVCC and VDRIVE pins on the AD7606/AD7606-6/AD7606-4 should use as large a trace as possible to provide low impedance paths and reduce the effect of glitches on the power supply lines. Where possible, use supply planes and make good connections between the AD7606 supply pins and the power tracks on the board. Use a single via or multiple vias for each supply pin. Good decoupling is also important to lower the supply impedance presented to the AD7606/AD7606-6/AD7606-4 and to reduce 055 the magnitude of the supply spikes. The decoupling capacitors 08479- should be placed close to (ideally, right up against) these pins Figure 63. Bottom Layer Decoupling and their corresponding ground pins. Place the decoupling capacitors for the REFIN/REFOUT pin and the REFCAPA and REFCAPB pins as close as possible to their respective AD7606/ AD7606-6/AD7606-4 pins; and, where possible, they should be placed on the same side of the board as the AD7606 device. Rev. C | Page 32 of 36 Document Outline Features Applications Functional Block Diagram Revision History General Description Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Terminology Theory of Operation Converter Details Analog Input Analog Input Ranges Analog Input Impedance Analog Input Clamp Protection Analog Input Antialiasing Filter Track-and-Hold Amplifiers ADC Transfer Function Internal/External Reference Typical Connection Diagram Power-Down Modes Conversion Control Simultaneous Sampling on All Analog Input Channels Simultaneously Sampling Two Sets of Channels Digital Interface Parallel Interface (PAR/SER/BYTE SEL = 0) Parallel Byte (PAR/SER/BYTE SEL = 1, DB15 = 1) Serial Interface (PAR/SER/BYTE SEL = 1) Reading During Conversion Digital Filter Layout Guidelines Outline Dimensions Ordering Guide