Datasheet AD9269 (Analog Devices) - 10

Data Sheet AD9269 TIMING SPECIFICATIONS Table 5. Parameter Test Conditions/Comments Min Typ Max Unit
SYNC TIMING REQUIREMENTS tSSYNC SYNC to rising edge of CLK setup time 0.24 ns tHSYNC SYNC to rising edge of CLK hold time 0.40 ns SPI TIMING REQUIREMENTS tDS Setup time between the data and the rising edge of SCLK 2 ns tDH Hold time between the data and the rising edge of SCLK 2 ns tCLK Period of the SCLK 40 ns tS Setup time between CSB and SCLK 2 ns tH Hold time between CSB and SCLK 2 ns tHIGH SCLK pulse width high 10 ns tLOW SCLK pulse width low 10 ns tEN_SDIO Time required for the SDIO pin to switch from an input to an 10 ns output relative to the SCLK falling edge tDIS_SDIO Time required for the SDIO pin to switch from an output to an 10 ns input relative to the SCLK rising edge
CLK+ t t SSYNC HSYNC SYNC
004 08538- Figure 4. SYNC Input Timing Requirements Rev. A | Page 9 of 40 Document Outline Features Applications Functional Block Diagram Product Highlights Revision History General Description Specifications DC Specifications AC Specifications Digital Specifications Switching Specifications Timing Specifications Absolute Maximum Ratings Thermal Characteristics ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics AD9269-80 AD9269-65 AD9269-40 AD9269-20 Equivalent Circuits Theory of Operation ADC Architecture Analog Input Considerations Input Common Mode Differential Input Configurations Single-Ended Input Configuration Voltage Reference Internal Reference Connection External Reference Operation Clock Input Considerations Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations Power Dissipation and Standby Mode Digital Outputs Digital Output Enable Function (OEB) Timing Data Clock Output (DCO) Built-In Self-Test (BIST) and Output Test Built-In Self-Test (BIST) Output Test Modes Channel/Chip Synchronization DC and Quadrature Error Correction (QEC) LO Leakage (DC) Correction QEC and DC Correction Range Serial Port Interface (SPI) Configuration Using the SPI Hardware Interface Configuration Without the SPI SPI Accessible Features Memory Map Reading the Memory Map Register Table Open Locations Default Values Logic Levels Transfer Register Map Channel-Specific Registers Memory Map Register Table Memory Map Register Descriptions Sync Control (Register 0x100) Bit 1—Clock Divider Sync Enable Bit 0—Master Sync Enable USR2 (Register 0x101) Bit 7—Enable OEB (Pin 47) Bits [6:4]—Open Bit 3—Enable GCLK Detect Bit 2—Run GCLK Bit 1—Open Bit 0—Disable SDIO Pull-Down QEC Control 0 (Register 0x110) Bits[7:6]—Open Bits[5:3]—Freeze DC/Freeze Phase/Freeze Gain Bits[2:0]—DC Enable/Phase Enable/Gain Enable QEC Control 1 (Register 0x111) Bits[7:3]—Open Bit 2—Force DC Bit 1—Force Phase Bit 0—Force Gain QEC Gain Bandwidth Control (Register 0x112) Bits[7:5]—Open Bits[4:0]—KEXP_GAIN QEC Phase Bandwidth Control (Register 0x113) Bits[7:5]—Open Bits[4:0]—KEXP_PHASE QEC DC Bandwidth Control (Register 0x114) Bits[7:5]—Open Bits[4:0]—KEXP_DC QEC Initial Gain 0, QEC Initial Gain 1 (Register 0x116 and Register 0x117) Bits[14:0]—Initial Gain QEC Initial Phase 0, QEC Initial Phase 1 (Register 0x118 and Register 0x119) Bits[12:0]—Initial Phase QEC Initial DC I 0, QEC Initial DC I 1 (Register 0x11A and Register 0x11B) Bits[13:0]—Initial DC I QEC Initial DC Q 0, QEC Initial DC Q 1 (Register 0x11C and Register 0x11D) Bits[13:0]—Initial DC Q Applications Information Design Guidelines Power and Ground Recommendations Exposed Paddle Thermal Heat Sink Recommendations VCM RBIAS Reference Decoupling SPI Port Outline Dimensions Ordering Guide