Datasheet AD9255 (Analog Devices) - 10

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Data Sheet AD9255 TIMING SPECIFICATIONS Table 5. Parameter Conditions Min Typ Max Unit
SYNC TIMING REQUIREMENTS tSSYNC SYNC to rising edge of CLK setup time 0.30 ns tHSYNC SYNC to rising edge of CLK hold time 0.40 ns SPI TIMING REQUIREMENTS1 tDS Setup time between the data and the rising edge of SCLK 2 ns tDH Hold time between the data and the rising edge of SCLK 2 ns tCLK Period of the SCLK 40 ns tS Setup time between CSB and SCLK 2 ns tH Hold time between CSB and SCLK 2 ns tHIGH SCLK pulse width high 10 ns tLOW SCLK pulse width low 10 ns tEN_SDIO Time required for the SDIO pin to switch from an input to an 10 ns output relative to the SCLK falling edge tDIS_SDIO Time required for the SDIO pin to switch from an output to an 10 ns input relative to the SCLK rising edge 1 Refer to Figure 84 for a detailed timing diagram.
Timing Diagrams N – 1 N + 4 tA N + 5 N N + 3 VIN N + 1 N + 2 tCH tCL tCLK CLK+ CLK– tDCO DCO/DCO+ DCO– tSKEW LVDS (DDR) MODE tPD D0/1+ TO D12/D13+ DEx DOx DEx DOx DEx DOx DEx DOx DEx DOx D0/1– TO D12/D13– – 12 – 12 – 11 – 11 – 10 – 10 – 9 – 9 – 8 – 8 CMOS MODE D0 TO D13 Dx – 12 Dx – 11 Dx – 10 Dx – 9 Dx – 8 NOTES
002
1. DEx DENOTES EVEN BIT. 2. DOx DENOTES ODD BIT.
08505- Figure 2. LVDS (DDR) and CMOS Output Mode Data Output Timing
CLK+ t t SSYNC HSYNC SYNC
104 08505- Figure 3. SYNC Input Timing Requirements Rev. C | Page 9 of 44 Document Outline Features Applications Product Highlights Functional Block Diagram Table of Contents Revision History General Description Specifications ADC DC Specifications ADC AC Specifications Digital Specifications Switching Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings Thermal Characteristics ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Equivalent Circuits Theory of Operation ADC Architecture Analog Input Considerations Input Common Mode Dither Differential Input Configurations Voltage Reference Internal Reference Connection External Reference Operation Clock Input Considerations Clock Input Options Clock Duty Cycle Input Clock Divider Jitter Considerations Power Dissipation and Standby Mode Digital Outputs Digital Output Enable Function (OEB) Timing Data Clock Output (DCO) Built-In Self-Test (BIST) and Output Test Built-In Self-Test (BIST) Output Test Modes Serial Port Interface (SPI) Configuration Using the SPI Hardware Interface Configuration Without the SPI SPI Accessible Features Memory Map Reading the Memory Map Register Table Open Locations Default Values Logic Levels Transfer Register Map Memory Map Register Table Memory Map Register Descriptions Sync Control (Register 0x100) Applications Information Design Guidelines Power and Ground Recommendations LVDS Operation Exposed Paddle Thermal Heat Slug Recommendations VCM RBIAS Reference Decoupling SPI Port Outline Dimensions Ordering Guide