Datasheet AD9268 (Analog Devices) - 3

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AD9268 TABLE OF CONTENTS
Features .. 1 Clock Input Considerations .. 30 Applications ... 1 Channel/Chip Synchronization .. 31 Functional Block Diagram .. 1 Power Dissipation and Standby Mode .. 32 Product Highlights ... 1 Digital Outputs ... 32 Revision History ... 2 Timing ... 33 General Description ... 3 Built-In Self-Test (BIST) and Output Test .. 34 Specifications ... 4 Built-In Self-Test (BIST) .. 34 ADC DC Specifications ... 4 Output Test Modes ... 34 ADC AC Specifications ... 6 Serial Port Interface (SPI) .. 35 Digital Specifications ... 7 Configuration Using the SPI ... 35 Switching Specifications .. 9 Hardware Interface ... 36 Timing Specifications .. 10 Configuration Without the SPI .. 36 Absolute Maximum Ratings .. 12 SPI Accessible Features .. 36 Thermal Characteristics .. 12 Memory Map .. 37 ESD Caution .. 12 Reading the Memory Map Register Table ... 37 Pin Configurations and Function Descriptions ... 13 Memory Map Register Table ... 38 Typical Performance Characteristics ... 17 Memory Map Register Descriptions .. 40 Equivalent Circuits ... 25 Applications Information .. 41 Theory of Operation .. 26 Design Guidelines .. 41 ADC Architecture .. 26 Outline Dimensions ... 42 Analog Input Considerations .. 26 Ordering Guide .. 42 Voltage Reference ... 29
REVISION HISTORY 9/09—Rev. 0 to Rev. A
Changes to Features List .. 1 Changes to Specifications Section .. 4 Changes to Table 5 .. 10 Changes to Typical Performance Characteristics Section ... 17
5/09—Revision 0: Initial Version
Rev. A | Page 2 of 44 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS ADC DC SPECIFICATIONS ADC AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Input Common Mode Common-Mode Voltage Servo Dither Differential Input Configurations VOLTAGE REFERENCE Internal Reference Connection External Reference Operation CLOCK INPUT CONSIDERATIONS Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations CHANNEL/CHIP SYNCHRONIZATION POWER DISSIPATION AND STANDBY MODE DIGITAL OUTPUTS Digital Output Enable Function (OEB) TIMING Data Clock Output (DCO) BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST BUILT-IN SELF-TEST (BIST) OUTPUT TEST MODES SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open Locations Default Values Logic Levels Transfer Register Map Channel-Specific Registers MEMORY MAP REGISTER TABLE MEMORY MAP REGISTER DESCRIPTIONS Sync Control (Register 0x100) Bits[7:3]—Reserved Bit 2—Clock Divider Next Sync Only Bit 1—Clock Divider Sync Enable Bit 0—Master Sync Enable APPLICATIONS INFORMATION DESIGN GUIDELINES Power and Ground Recommendations LVDS Operation Exposed Paddle Thermal Heat Slug Recommendations VCM RBIAS Reference Decoupling SPI Port OUTLINE DIMENSIONS ORDERING GUIDE