Datasheet AD7191 (Analog Devices) - 7

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AD7191 TIMING CHARACTERISTICS
AVDD = 3 V to 5.25 V; DVDD = 2.7 V to 5.25 V; AGND = DGND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = DVDD, unless otherwise noted.
Table 2. Parameter1, 2 Limit at TMIN, TMAX (B Version) Unit Conditions/Comments
t3 100 ns min SCLK high pulse width t4 100 ns min SCLK low pulse width Read Operation t1 0 ns min PDOWN falling edge to DOUT/RDY active time 60 ns max DVDD = 4.75 V to 5.25 V 80 ns max DVDD = 2.7 V to 3.6 V t 3 2 0 ns min SCLK active edge to data valid delay4 60 ns max DVDD = 4.75 V to 5.25 V 80 ns max DVDD = 2.7 V to 3.6 V t 5, 6 5 10 ns min Bus relinquish time after PDOWN inactive edge 80 ns max t6 0 ns min SCLK inactive edge to PDOWN inactive edge t7 10 ns min SCLK inactive edge to DOUT/RDY high 1 Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.6 V. 2 See Figure 3. 3 These numbers are measured with the load circuit shown in Figure 2 and defined as the time required for the output to cross the VOL or VOH limits. 4 The SCLK active edge is the falling edge of SCLK. 5 These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit shown in Figure 2. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the part and, as such, are independent of external bus loading capacitances. 6 RDY returns high after a read of the ADC. The digital word can be read only once.
ISINK (1.6mA WITH DVDD = 5V, 100µA WITH DVDD = 3V) TO OUTPUT 1.6V PIN 50pF
2
I
00
SOURCE (200µA WITH DVDD = 5V,
3-
100µA WITH DVDD = 3V)
16 08 Figure 2. Load Circuit for Timing Characterization
TIMING DIAGRAM PDOWN (I) t t 1 t 5 6 DOUT/RDY (O) t2 t7 t3 SCLK (I) t4
3 00 3-
NOTES
16 08
1. I = INPUT, O = OUTPUT
Figure 3. Read Cycle Timing Diagram Rev. A | Page 6 of 20 Document Outline FEATURES INTERFACE APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING CHARACTERISTICS TIMING DIAGRAM ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS RMS NOISE AND RESOLUTION SPECIFICATIONS ADC CIRCUIT INFORMATION OVERVIEW FILTER, DATA RATE, AND SETTLING TIME GAIN ANALOG INPUT CHANNELS TEMPERATURE SENSOR POWER-DOWN (PDOWN) CLOCK BIPOLAR CONFIGURATION DATA OUTPUT CODING BRIDGE POWER-DOWN SWITCH REFERENCE DIGITAL INTERFACE GROUNDING AND LAYOUT APPLICATIONS INFORMATION WEIGH SCALES EMI RECOMMENDATIONS OUTLINE DIMENSIONS ORDERING GUIDE