Datasheet AD7682, AD7689 (Analog Devices) - 31

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Data Sheet AD7682/AD7689 READ/WRITE SPANNING CONVERSION WITHOUT
host also must enable the MSB of the CFG register at this time
A BUSY INDICATOR
(if necessary) to begin the CFG update. While CNV is low, both a CFG update and a data readback take place. The first 14 SCK This mode is used when the AD7682/AD7689 are connected to rising edges are used to update the CFG, and the first 15 SCK any host using an SPI, serial port, or FPGA. The connection falling edges clock out the conversion results starting with diagram is shown in Figure 42, and the corresponding timing is MSB − 1. The restriction for both configuring and reading is given in Figure 43. For the SPI, the host must use CPHA = that they both must occur before the t CPOL = 0. Reading/writing spanning conversion is shown, DATA time of the next conversion elapses. All 14 bits of CFG[13:0] must be written or which covers all three modes detailed in the Digital Interface they are ignored. In addition, if the 16-bit conversion result is section. For this mode, the host must generate the data transfer not read back before t based on the conversion time. For an interrupt driven transfer DATA elapses, it is lost. that uses a busy indicator, refer to the Read/Write Spanning The SDO data is valid on both SCK edges. Although the rising Conversion with a Busy Indicator section. edge can capture the data, a digital host using the SCK falling edge allows a faster reading rate, provided it has an acceptable A rising edge on CNV initiates a conversion, forces SDO to hold time. After the 16th (or 30th) SCK falling edge, or when high impedance, and ignores data present on DIN. After a CNV goes high (whichever occurs first), SDO returns to high conversion initiates, it continues until completion, irrespective impedance. of the state of CNV. CNV must be returned high before the safe data transfer time (tDATA), and held high beyond the conversion If CFG readback is enabled, the CFG register associated with time (tCONV) to avoid generation of the busy signal indicator. the conversion result is read back MSB first following the LSB of the conversion result. A total of 30 SCK falling edges is required After the conversion is complete, the AD7682/AD7689 enter to return SDO to high impedance if this is enabled. the acquisition phase and power-down. When the host brings CNV low after tCONV (maximum), the MSB enables on SDO. The
AD7682/ DIGITAL HOST AD7689 CNV SS SDO MISO DIN MOSI SCK SCK
36 -0 353
FOR SPI USE CPHA = 0, CPOL = 0.
07 Figure 42. Connection Diagram for the AD7682/AD7689 Without a Busy Indicator
tCYC > tCONV t t CONV CONV t t DATA DATA t EOC CNVH EOC RETURN CNV HIGH RETURN CNV HIGH CNV FOR NO BUSY FOR NO BUSY tACQ ACQUISITION (QUIET (QUIET CONVERSION (n – 1) ACQUISITION (n) (n - 1) CONVERSION (n) TIME) TIME) tSCK UPDATE (n) UPDATE (n + 1) tSCKH CFG/SDO SEE NOTE CFG/SDO SCK 14 15 16/ 1 2 14 15 16/ 30 30 t t CLSCK SCKL t t SDIN HDIN CFG CFG CFG DIN X X X X LSB MSB LSB t tEN END CFG (n) tEN BEGIN CFG (n + 1) HSDO t END CFG (n + 1) EN tDSDO SEE NOTE SDO LSB MSB LSB tDIS END DATA (n – 2) tDIS BEGIN DATA (n – 1) t END DATA (n – 1) t DIS DIS NOTES 1. THE LSB IS FOR CONVERSION RESULTS OR THE CONFIGURATION REGISTER CFG (n – 1) IF
37
15 SCK FALLING EDGES = LSB OF CONVERSION RESULTS.
0
29 SCK FALLING EDGES = LSB OF CONFIGURATION REGISTER.
353-
ON THE 16TH OR 30TH SCK FALLING EDGE, SDO IS DRIVEN TO HIGH IMPENDANCE.
07 Figure 43. Serial Interface Timing for the AD7682/AD7689 Without a Busy Indicator Rev. H | Page 31 of 35 Document Outline Features Applications Functional Block Diagram General Description Table of Contents Revision History Specifications Timing Specifications Absolute Maximum Ratings ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Terminology Theory of Operation Overview Converter Operation Transfer Functions Typical Connection Diagrams Unipolar or Bipolar Bipolar Single Supply Analog Inputs Input Structure Selectable Low-Pass Filter Input Configurations Sequencer Source Resistance Driver Amplifier Choice Voltage Reference Output/Input Internal Reference/Temperature Sensor External Reference and Internal Buffer External Reference Reference Decoupling Power Supply Supplying the ADC from the Reference Digital Interface Reading/Writing During Conversion, Fast Hosts Reading/Writing After Conversion, Any Speed Hosts Reading/Writing Spanning Conversion, Any Speed Host Configuration Register, CFG General Timing Without a Busy Indicator General Timing with a Busy Indicator Channel Sequencer Examples Read/Write Spanning Conversion Without a Busy Indicator Read/Write Spanning Conversion with a Busy Indicator Applications Information Layout Evaluating the AD7682/AD7689 Performance Outline Dimensions Ordering Guide