link to page 15 Data SheetAD7264ParameterMinTypMaxUnitTest Conditions/Comments POWER REQUIREMENTS Digital inputs = 0 V or VDRIVE AVCC 4.75 5.25 V CA_CBVCC, CC_CDVCC 2.7 5.25 V VDRIVE 2.7 5.25 V IDD ADC Normal Mode (Static) 20 31.5 mA AVCC = 5.25 V ADC Normal Mode (Dynamic) 23 33.3 mA fS = 1 MSPS, AVCC = 5.25 V Shutdown Mode 0.5 1 μA AVCC = 5.25 V, ADCs and comparators powered down Power Dissipation ADC Normal Mode (Static) 105 165 mW ADC Normal Mode (Dynamic) 120 175 mW Shutdown Mode 2.625 5.25 µW 1 These specifications were determined without the use of the gain calibration feature. 2 See the Terminology section. 3 Samples are tested during initial release to ensure compliance; they are not subject to production testing. 4 For PGA gain = 1, to utilize the full analog input range (VCM ± VREF/2) of the AD7264, the VCM voltage should be dropped to lie within a range from 1.95 V to 2.05 V. 5 Refers to Pin VREFA or Pin VREFB. 6 This specification includes the IDD for both comparators. The IDD per comparator is the specified value divided by 2. Rev. D | Page 5 of 29 Document Outline FEATURES GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CIRCUIT INFORMATION COMPARATORS OPERATION ANALOG INPUTS Transfer Function VDRIVE REFERENCE TYPICAL CONNECTION DIAGRAMS Comparator Application Details APPLICATION DETAILS MODES OF OPERATION PIN DRIVEN MODE GAIN SELECTION POWER-DOWN MODES Power-Up Conditions CONTROL REGISTER ON-CHIP REGISTERS Writing to a Register Reading from a Register SERIAL INTERFACE CALIBRATION INTERNAL OFFSET CALIBRATION ADJUSTING THE OFFSET CALIBRATION REGISTER SYSTEM GAIN CALIBRATION APPLICATIONS INFORMATION GROUNDING AND LAYOUT PCB DESIGN GUIDELINES FOR LFCSP OUTLINE DIMENSIONS ORDERING GUIDE
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