Datasheet AD9626 (Analog Devices) - 8

AD9626 TIMING DIAGRAMS N + 2 N + 1 N + 3 N N + 4 N + 8 tA N + 5 N + 6 N + 7 tCLK = 1/fCLK CLK+ CLK– tCPD DCO– DCO+ tSKEW tPD
51 0
DAX N – 7 N – 6 N – 5 N – 4 N – 3 N – 2 N – 1 N N + 1 N + 2
9-09 07 Figure 2. Single Port Mode
N + 2 N + 1 N + 3 N N + 4 N + 8 tA N + 5 N + 7 N + 6 tCLK = 1/fCLK CLK+ CLK– tCPDA tCPDB DCO+ DCO– tSKEWA tPDA DAX N – 6 N – 4 N – 2 N N + 2 tSKEWB tPDB
0 5 0
DBX N – 7 N – 5 N – 3 N – 1 N + 1
9- 09 07 Figure 3. Interleaved Mode Rev. 0 | Page 7 of 36 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS EQUIVALENT CIRCUITS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION ANALOG INPUT AND VOLTAGE REFERENCE Differential Input Configurations CLOCK INPUT CONSIDERATIONS Clock Duty Cycle Considerations Clock Jitter Considerations POWER DISSIPATION AND POWER-DOWN MODE DIGITAL OUTPUTS Digital Outputs and Timing Out-of-Range TIMING—SINGLE PORT MODE TIMING—INTERLEAVED MODE fS/2 Spurious LAYOUT CONSIDERATIONS POWER AND GROUND RECOMMENDATIONS Exposed Paddle Thermal Heat Slug Recommendations CML RBIAS AD9626 CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI MEMORY MAP READING THE MEMORY MAP TABLE RESERVED LOCATIONS DEFAULT VALUES LOGIC LEVELS EVALUATION BOARD OUTLINE DIMENSIONS ORDERING GUIDE