Datasheet AD7766 (Analog Devices) - 8

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AD7766 PART OUT OF POWER-DOWN FILTER RESET PART IN POWER-DOWN BEGINS SAMPLING MCLK (I) A B C D t t 18 20 SYNC/PD (I) t t 19 21 DRDY (O) tSETTLING
5 00 9-
SDO (O) VALID DATA INVALID DATA VALID DATA
44 06 Figure 5. Reset, Synchronization, and Power-Down Timing (For More Information, See the Power-Down, Reset, and Synchronization Section) Rev. C | Page 7 of 24 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION RELATED DEVICES TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION AD7766/AD7766-1/AD7766-2 TRANSFER FUNCTION CONVERTER OPERATION ANALOG INPUT STRUCTURE SUPPLY AND REFERENCE VOLTAGES AD7766/AD7766-1/AD77662-2 INTERFACE INITIAL POWER-UP READING DATA POWER-DOWN, RESET, AND SYNCHRONIZATION DAISY CHAINING READING DATA IN DAISY-CHAIN MODE CHOOSING THE SCLK FREQUENCY DAISY-CHAIN MODE CONFIGURATION AND TIMING DIAGRAMS DRIVING THE AD7766/AD7766-1/AD7766-2 DIFFERENTIAL SIGNAL SOURCE SINGLE-ENDED SIGNAL SOURCE ANTIALIASING POWER DISSIPATION VREF+ INPUT SIGNAL MULTIPLEXING ANALOG INPUT CHANNELS OUTLINE DIMENSIONS ORDERING GUIDE