Datasheet AD9211 (Analog Devices) - 7

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AD9211 SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = −40°C, TMAX = +85°C, fIN = −1.0 dBFS, full scale = 1.25 V, DCS enabled, unless otherwise noted.
Table 4. AD9211-200 AD9211-250 AD921-300 Parameter (Conditions) Temp Min Typ Max Min Typ Max Min Typ Max Unit
Maximum Conversion Rate Full 200 250 300 MSPS Minimum Conversion Rate Full 40 40 40 MSPS CLK+ Pulse Width High (tCH) Full 2.25 2.5 1.8 2.0 1.5 1.7 ns CLK+ Pulse Width Low (tCL) Full 2.25 2.5 1.8 2.0 1.5 1.7 ns Output (LVDS − SDR Mode)1 Data Propagation Delay (tPD) Full 3.0 3.0 3.0 ns Rise Time (tR) (20% to 80%) 25°C 0.2 0.2 0.2 ns Fall Time (tF) (20% to 80%) 25°C 0.2 0.2 0.2 ns DCO Propagation Delay (tCPD) Full 3.9 3.9 3.9 ns Data to DCO Skew (tSKEW) Full −0.3 +0.1 +0.5 −0.3 +0.1 +0.5 −0.3 +0.1 +0.5 ns Latency Full 7 7 7 Cycles Output (LVDS − DDR Mode)2 Data Propagation Delay (tPD) Full 3.8 3.8 3.8 ns Rise Time (tR) (20% to 80%) 25°C 0.2 0.2 0.2 ns Fall Time (tF) (20% to 80%) 25°C 0.2 0.2 0.2 ns DCO Propagation Delay (tCPD) Full 3.9 3.9 3.9 ns Data to DCO Skew (tSKEW) Full −0.5 +0.1 +0.3 −0.5 +0.1 +0.3 −0.5 +0.1 +0.3 ns Latency Full 7 7 7 Cycles Aperture Uncertainty (Jitter, tJ) 25°C 0.2 0.2 ps rms 1 See Figure 2. 2 See Figure 3. Rev. 0 | Page 6 of 28 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS THEORY OF OPERATION ANALOG INPUT AND VOLTAGE REFERENCE Differential Input Configurations CLOCK INPUT CONSIDERATIONS Clock Duty Cycle Considerations Clock Jitter Considerations POWER DISSIPATION AND POWER-DOWN MODE DIGITAL OUTPUTS Digital Outputs and Timing Output Data Rate and Pinout Configuration Out-of-Range (OR) TIMING RBIAS AD9211 CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI MEMORY MAP READING THE MEMORY MAP TABLE RESERVED LOCATIONS DEFAULT VALUES LOGIC LEVELS OUTLINE DIMENSIONS ORDERING GUIDE