Datasheet AD9254 (Analog Devices) - 10

AD9254 EQUIVALENT CIRCUITS 1kΩ SCLK/DFS VIN OEB PDWN 30kΩ
4 8 00 00 6- 6- 21 21 06 06 Figure 4. Equivalent Analog Input Circuit Figure 8. Equivalent SCLK/DFS, OEB, PDWN Input Circuit
AVDD AVDD 1.2V 26kΩ 1kΩ CSB 10kΩ 10kΩ CLK+ CLK–
5 09 0 -00 6 6- 21 21 06 06 Figure 5. Equivalent Clock Input Circuit Figure 9. Equivalent CSB Input Circuit
DRVDD 1kΩ SENSE 1kΩ SDIO/DCS
6 10 0 00 6- 6- 21 21 06 06 Figure 6. Equivalent SDIO/DCS Input Circuit Figure 10. Equivalent Sense Circuit
DRVDD AVDD VREF
1
6kΩ
01 7 6- 00 21 6-
DRGND
06 21 06 Figure 11. Equivalent VREF Circuit Figure 7. Equivalent Digital Output Circuit Rev. 0 | Page 9 of 40 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING DIAGRAM ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS EQUIVALENT CIRCUITS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION ANALOG INPUT CONSIDERATIONS DIFFERENTIAL INPUT CONFIGURATIONS VOLTAGE REFERENCE CLOCK INPUT CONSIDERATIONS JITTER CONSIDERATIONS POWER DISSIPATION AND STANDBY MODE DIGITAL OUTPUTS TIMING SERIAL PORT INTERFACE (SPI) MEMORY MAP READING THE MEMORY MAP REGISTER TABLE MEMORY MAP REGISTER TABLE LAYOUT CONSIDERATIONS POWER AND GROUND RECOMMENDATIONS CML RBIAS REFERENCE DECOUPLING EVALUATION BOARD POWER SUPPLIES INPUT SIGNALS OUTPUT SIGNALS DEFAULT OPERATION AND JUMPER SELECTION SETTINGS ALTERNATIVE CLOCK CONFIGURATIONS ALTERNATIVE ANALOG INPUT DRIVE CONFIGURATION SCHEMATICS EVALUATION BOARD LAYOUT BILL OF MATERIALS OUTLINE DIMENSIONS ORDERING GUIDE