Datasheet AD9252 (Analog Devices) - 8

Data Sheet AD9252 TIMING DIAGRAMS N – 1 VIN ± x tA N tEH tEL CLK– CLK+ tCPD DCO– DCO+ t t FCO FRAME FCO– FCO+ tPD tDATA D – x MSB D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 MSB D12
2
N – 9 N – 9 N – 9 N – 9 N – 9 N – 9 N – 9 N – 9 N – 9 N – 9 N – 9 N – 9 N – 9 N – 9 N – 8 N – 8
00 6-
D + x
629 0 Figure 2. 14-Bit Data Serial Stream (Default), MSB First
N – 1 VIN ± x tA N tEH tEL CLK– CLK+ tCPD DCO– DCO+ t t FCO FRAME FCO– FCO+ tPD tDATA D – x MSB D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 MSB D10 N – 9 N – 9 N – 9 N – 9 N – 9 N – 9 N – 9 N – 9 N – 9 N – 9 N – 9 N – 9 N – 8 N – 8
3 00
D + x
6- 29 06 Figure 3. 12-Bit Data Serial Stream, MSB First Rev. E | Page 7 of 52 Document Outline Features Applications General Description Functional Block Diagram Product Highlights Revision History Specifications AC Specifications Digital Specifications Switching Specifications Timing Diagrams Absolute Maximum Ratings Thermal Impedance ESD Caution Pin Configuration and Function Descriptions Equivalent Circuits Typical Performance Characteristics Theory of Operation Analog Input Considerations Differential Input Configurations Single-Ended Input Configuration Clock Input Considerations Clock Duty Cycle Considerations Clock Jitter Considerations Power Dissipation and Power-Down Mode Digital Outputs and Timing SDIO/ODM Pin SCLK/DTP Pin CSB Pin RBIAS Pin Voltage Reference Internal Reference Operation External Reference Operation Serial Port Interface (SPI) Hardware Interface Memory Map Reading the Memory Map Table Reserved Locations Default Values Logic Levels Applications Information Design Guidelines Power and Ground Recommendations Exposed Paddle Thermal Heat Slug Recommendations Evaluation Board Power Supplies Input Signals Output Signals Default Operation and Jumper Selection Settings Alternative Analog Input Drive Configuration Outline Dimensions Ordering Guide