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Datasheet AD9222 (Analog Devices) - 4

ПроизводительAnalog Devices
ОписаниеOctal, 12-Bit, 40/50/65 MSPS Serial LVDS 1.8 V A/D Converter
Страниц / Страница61 / 4 — Data Sheet. AD9222. SPECIFICATIONS. Table 1. AD9222-40. AD9222-50. …
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Data Sheet. AD9222. SPECIFICATIONS. Table 1. AD9222-40. AD9222-50. AD9222-65. Parameter. Temp Min. Typ. Max. Min. Unit

Data Sheet AD9222 SPECIFICATIONS Table 1 AD9222-40 AD9222-50 AD9222-65 Parameter Temp Min Typ Max Min Unit

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Data Sheet AD9222 SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.
Table 1. AD9222-40 AD9222-50 AD9222-65 Parameter
1
Temp Min Typ Max Min Typ Max Min Typ Max Unit
RESOLUTION 12 12 12 Bits ACCURACY No Missing Codes Full Guaranteed Guaranteed Guaranteed Offset Error Full ±1 ±8 ±1 ±8 ±1 ±8 mV Offset Matching Full ±3 ±8 ±3 ±8 ±3 ±8 mV Gain Error Full ±0.4 ±1.2 ±1.5 ±2.5 ±3.5 ±5 % FS Gain Matching Full ±0.3 ±0.7 ±0.3 ±0.7 ±0.4 ±0.8 % FS Differential Nonlinearity (DNL) Full ±0.25 ±0.5 ±0.3 ±0.65 ±0.25 ±0.6 LSB Integral Nonlinearity (INL) Full ±0.4 ±1 ±0.4 ±1 ±0.4 ±1 LSB TEMPERATURE DRIFT Offset Error Full ±2 ±2 ±2 ppm/°C Gain Error Full ±17 ±17 ±17 ppm/°C Reference Voltage (1 V Mode) Full ±21 ±21 ±21 ppm/°C REFERENCE Output Voltage Error (VREF = 1 V) Full ±2 ±30 ±2 ±30 ±2 ±30 mV Load Regulation @ 1.0 mA (VREF = 1 V) Full 3 3 3 mV Input Resistance Full 6 6 6 kΩ ANALOG INPUTS Differential Input Voltage Range Full 2 2 2 V p-p (VREF = 1 V) Common-Mode Voltage Full AVDD/2 AVDD/2 AVDD/2 V Differential Input Capacitance Full 7 7 7 pF Analog Bandwidth, Full Power Full 325 325 325 MHz POWER SUPPLY AVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V DRVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V IAVDD Full 338 348.5 357.5 367.5 450 470 mA IDRVDD Full 51 53.6 53.5 56.2 56.6 60.5 mA Total Power Dissipation Full 700 722 740 760 910 950.5 mW (Including Output Drivers) Power-Down Dissipation Full 2 11 2 11 2 11 mW Standby Dissipation2 Full 83 89 100 mW CROSSTALK Full −90 −90 −90 dB CROSSTALK (Overrange Condition)3 Full −90 −90 −90 dB 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed. 2 This can be controlled via SPI. 3 Overrange condition is specific with 6 dB of the ful -scale input range. Rev. F | Page 3 of 60 Document Outline Features Applications General Description Functional Block Diagram Product Highlights Table of Contents Revision History Specifications AC Specifications Digital Specifications Switching Specifications Timing Diagrams Absolute Maximum Ratings Thermal Impedance ESD Caution Pin Configuration and Function Descriptions Equivalent Circuits Typical Performance Characteristics Theory of Operation Analog Input Considerations Differential Input Configurations Single-Ended Input Configuration Clock Input Considerations Clock Duty Cycle Considerations Clock Jitter Considerations Power Dissipation and Power-Down Mode Digital Outputs and Timing SDIO/ODM Pin SCLK/DTP Pin CSB Pin RBIAS Pin Voltage Reference Internal Reference Operation External Reference Operation Serial Port Interface (SPI) Hardware Interface Memory Map Reading the Memory Map Table Reserved Locations Default Values Logic Levels Power and Ground Recommendations Exposed Paddle Thermal Heat Slug Recommendations Evaluation Board Power Supplies Input Signals Output Signals Default Operation and Jumper Selection Settings Alternative Analog Input Drive Configuration Outline Dimensions Ordering Guide
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