Datasheet AD7951 (Analog Devices) - 11

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AD7951 Data Sheet Pin No. Mnemonic Type1 Description
23 D8 or DO In parallel mode, this output is used as Bit 8 of the parallel port data output bus. SYNC Serial Data Frame Synchronization. In serial master mode (SER/PAR = high, EXT/INT= low), this output is used as a digital output frame synchronization for use with the internal data clock. When a read sequence is initiated and INVSYNC = low, SYNC is driven high and remains high while the SDOUT output is valid. When a read sequence is initiated and INVSYNC = high, SYNC is driven low and remains low while the SDOUT output is valid. 24 D9 or DO In parallel mode, this output is used as Bit 9 of the parallel port data output bus. RDERROR Serial Data Read Error. In serial slave mode (SER/PAR = high, EXT/INT = high), this output is used as an incomplete data read error flag. If a data read is started and not completed when the current conversion is complete, the current data is lost and RDERROR is pulsed high. 25 D10 or DI/O In parallel mode, this output is used as Bit 10 of the parallel port data output bus. HW/SW Serial Configuration Hardware/Software Select. In serial mode, this input is used to configure the AD7951 by hardware or software. See the Hardware Configuration section and Software Configuration section. When HW/SW = low, the AD7951 is configured through software using the serial configuration register. When HW/SW = high, the AD7951 is configured through dedicated hardware input pins. 26 D11 or DI/O In parallel mode, this output is used as Bit 11 of the parallel port data output bus. SCIN Serial Configuration Data Input. In serial software configuration mode (SER/PAR = high, HW/SW = low) this input is used to serially write in, MSB first, the configuration data into the serial configuration register. The data on this input is latched with SCCLK. See the Software Configuration section. 27 D12 or DI/O In parallel mode, this output is used as Bit 12 of the parallel port data output bus. SCCLK Serial Configuration Clock. In serial software configuration mode (SER/PAR = high, HW/SW = low) this input is used to clock in the data on SCIN. The active edge where the data SCIN is updated depends on the logic state of the INVSCLK pin. See the Software Configuration section. 28 D13 or DI/O In parallel mode, this output is used as Bit 13 of the parallel port data output bus. SCCS Serial Configuration Chip Select. In serial software configuration mode (SER/PAR = high, HW/SW = low) this input enables the serial configuration port. See the Software Configuration section. 29 BUSY DO Busy Output. Transitions high when a conversion is started, and remains high until the conversion is complete and the data is latched into the on-chip shift register. The falling edge of BUSY can be used as a data ready clock signal. Note that in master read after convert mode (SER/PAR = high, EXT/INT = low, RDC = low), the busy time changes according to Table 4. 30 TEN DI2 Input Range Select. Used in conjunction with BIPOLAR per the following:
Input Range BIPOLAR TEN
0 V to 5 V Low Low 0 V to 10 V Low High ±5 V High Low ±10 V High High 31 RD DI Read Data. When CS and RD are both low, the interface parallel or serial output bus is enabled. 32 CS DI Chip Select. When CS and RD are both low, the interface parallel or serial output bus is enabled. CS is also used to gate the external clock in slave serial mode (not used for serial programmable port). 33 RESET DI Reset Input. When high, reset the AD7951. Current conversion, if any, is aborted. The falling edge of RESET resets the data outputs to all zeros (with OB/2C = high) and clears the configuration register. See the Digital Interface section. If not used, this pin can be tied to OGND. 34 PD DI2 Power-Down Input. When PD = high, powers down the ADC. Power consumption is reduced and conversions are inhibited after the current one is completed. The digital interface remains active during power-down. 35 CNVST DI Conversion Start. A falling edge on CNVST puts the internal sample-and-hold into the hold state and initiates a conversion. 36 BIPOLAR DI2 Input Range Select. See description for Pin 30. Rev. B | Page 10 of 32 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION OVERVIEW CONVERTER OPERATION MODES OF OPERATION Normal Mode Impulse Mode TRANSFER FUNCTIONS TYPICAL CONNECTION DIAGRAM ANALOG INPUTS Input Range Selection Input Structure VOLTAGE REFERENCE INPUT/OUTPUT Internal Reference (REF = 5 V) (PDREF = Low, PDBUF = Low) External 2.5 V Reference and Internal Buffer (REF = 5 V) (PDREF = High, PDBUF = Low) External 5 V Reference (PDREF = High, PDBUF = High) Reference Decoupling Temperature Sensor POWER SUPPLIES Core Supplies High Voltage Supplies Digital Output Supply Power Sequencing Power Dissipation vs. Throughput Power Down CONVERSION CONTROL INTERFACES DIGITAL INTERFACE RESET PARALLEL INTERFACE Master Parallel Interface Slave Parallel Interface 8-Bit Interface (Master or Slave) SERIAL INTERFACE Data Interface Serial Configuration Interface MASTER SERIAL INTERFACE Internal Clock (SER/PAR = High, EXT/INT = Low) Read During Convert (RDC = High) Read After Convert (RDC = Low, DIVSCLK[1:0] = [0 to 3]) SLAVE SERIAL INTERFACE External Clock (SER/PAR = High, EXT/INT = High) External Discontinuous Clock Data Read After Conversion Daisy-Chain Feature External Clock Data Read During Previous Conversion External Clock Data Read After/During Conversion HARDWARE CONFIGURATION SOFTWARE CONFIGURATION MICROPROCESSOR INTERFACING SPI Interface APPLICATION INFORMATION LAYOUT GUIDELINES OUTLINE DIMENSIONS ORDERING GUIDE