Datasheet AD7951 (Analog Devices) - 31

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AD7951 Data Sheet WARP = 0 OR 1 BIP = 0 OR 1 SER/PAR = 1 INVSCLK = 0 IMPULSE = 0 OR 1 TEN = 0 OR 1 HW/SW = 0 t PD = 0 8 CNVST BUSY t31 SCCS t t 31 35 t36 SCCLK 1 2 3 4 5 6 7 8 9 t37 SCIN X START BIPOLAR TEN PD IMPULSE WARP OB/2C X t33
5 04 6-
t34
39 06 Figure 45. Serial Configuration Port Timing
MICROPROCESSOR INTERFACING
the DSP. The serial peripheral interface (SPI) on the ADSP-219x The AD7951 is ideally suited for traditional dc measurement is configured for master mode (MSTR) = 1, clock polarity bit applications supporting a microprocessor, and ac signal (CPOL) = 0, clock phase bit (CPHA) = 1, and SPI interrupt enable processing applications interfacing to a digital signal processor. (TIMOD) = 0 by writing to the SPI control register (SPICLTx). The AD7951 is designed to interface with a parallel 8-bit or It should be noted that to meet all timing requirements, the SPI 14-bit wide interface, or with a general-purpose serial port or clock should be limited to 17 Mbps, allowing it to read an ADC I/O ports on a microcontroller. A variety of external buffers can result in less than 1 μs. When a higher sampling rate is desired, be used with the AD7951 to prevent digital noise from coupling use one of the parallel interface modes. into the ADC.
DVDD SPI Interface AD7951* ADSP-219x*
The AD7951 is compatible with SPI and QSPI digital hosts and
SER/PAR
DSPs such as Blackfin® ADSP-BF53x and ADSP-218x/ADSP-219x.
BUSY PFx EXT/INT
Figure 46 shows an interface diagram between the AD7951 and
CS SPIxSEL (PFx) SDOUT MISOx
the SPI-equipped ADSP-219x. To accommodate the slower
RD SCLK SCKx
speed of the DSP, the AD7951 acts as a slave device, and data must
INVSCLK CNVST PFx OR TFSx
be read after conversion. This mode also allows the daisy-chain 46 0 6- feature. The convert command could be initiated in response to
*ADDITIONAL PINS OMITTED FOR CLARITY.
39 06 an internal timer interrupt. Figure 46. Interfacing the AD7951 to SPI Interface The reading process can be initiated in response to the end-of- conversion signal (BUSY going low) using an interrupt line of Rev. B | Page 30 of 32 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION OVERVIEW CONVERTER OPERATION MODES OF OPERATION Normal Mode Impulse Mode TRANSFER FUNCTIONS TYPICAL CONNECTION DIAGRAM ANALOG INPUTS Input Range Selection Input Structure VOLTAGE REFERENCE INPUT/OUTPUT Internal Reference (REF = 5 V) (PDREF = Low, PDBUF = Low) External 2.5 V Reference and Internal Buffer (REF = 5 V) (PDREF = High, PDBUF = Low) External 5 V Reference (PDREF = High, PDBUF = High) Reference Decoupling Temperature Sensor POWER SUPPLIES Core Supplies High Voltage Supplies Digital Output Supply Power Sequencing Power Dissipation vs. Throughput Power Down CONVERSION CONTROL INTERFACES DIGITAL INTERFACE RESET PARALLEL INTERFACE Master Parallel Interface Slave Parallel Interface 8-Bit Interface (Master or Slave) SERIAL INTERFACE Data Interface Serial Configuration Interface MASTER SERIAL INTERFACE Internal Clock (SER/PAR = High, EXT/INT = Low) Read During Convert (RDC = High) Read After Convert (RDC = Low, DIVSCLK[1:0] = [0 to 3]) SLAVE SERIAL INTERFACE External Clock (SER/PAR = High, EXT/INT = High) External Discontinuous Clock Data Read After Conversion Daisy-Chain Feature External Clock Data Read During Previous Conversion External Clock Data Read After/During Conversion HARDWARE CONFIGURATION SOFTWARE CONFIGURATION MICROPROCESSOR INTERFACING SPI Interface APPLICATION INFORMATION LAYOUT GUIDELINES OUTLINE DIMENSIONS ORDERING GUIDE