link to page 4 link to page 4 link to page 4 link to page 4 link to page 4 link to page 4 link to page 4 link to page 4 link to page 4 link to page 4 AD9460SPECIFICATIONS DC SPECIFICATIONS AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, LVDS mode, specified minimum sampling rate, 3.4 V p-p differential input, internal trimmed reference (1.0 V mode), analog input amplitude = −1.0 dBFS, DCS = AGND (on), SFDR = AGND, unless otherwise noted. Table 1.AD9460BSVZ-80AD9460BSVZ-105ParameterTempMin Typ Max Min Typ Max Unit RESOLUTION Full 16 16 Bits ACCURACY No Missing Codes Full Guaranteed Guaranteed Offset Error Full −5.0 ±0.1 +5.0 −5.0 ±0.1 +5.0 mV Gain Error 25°C −3 ±0.5 +3 −3 ±0.5 +3 % FSR Full −3.4 +3.4 −3.4 +3.4 % FSR Differential Nonlinearity (DNL)1 25°C −0.8 ±0.5 +0.8 −0.85 ±0.5 +0.85 LSB Full −0.9 +0.9 −1 +1.2 Integral Nonlinearity (INL)1 25°C −6 ±3 +6 −6 ±3 +6 LSB VOLTAGE REFERENCE Output Voltage VREF = 1.7 V Full 1.7 1.7 V Load Regulation @ 1.0 mA Full ±2 ±2 mV Reference Input Current (External VREF = 1.7 V) Full 350 350 μA INPUT REFERRED NOISE 25°C 2.4 2.5 LSB rms ANALOG INPUT Input Span VREF = 1.7 V Full 3.4 3.4 V p-p VREF = 1.0 V Full 2.0 2.0 V p-p Internal Input Common-Mode Voltage Full 3.5 3.5 V External Input Common-Mode Voltage Full 3.2 3.9 3.2 3.9 V Input Resistance2 Full 1 1 kΩ Input Capacitance2 Full 6 6 pF POWER SUPPLIES Supply Voltages AVDD1 Full 3.14 3.3 3.46 3.14 3.3 3.46 V AVDD2 Full 4.75 5.0 5.25 4.75 5.0 5.25 V DRVDD—LVDS Outputs Full 3.0 3.3 3.6 3.0 3.3 3.6 V DRVDD—CMOS Outputs Full 3.0 3.3 3.6 3.0 3.3 3.6 V Supply Currents1 AVDD1 Full 290 310 337 373 mA AVDD21, 3 Full 101 110 116 133 mA I 1 DRVDD —LVDS Outputs Full 70 78.5 71 81 mA I 1 DRVDD —CMOS Outputs Full 14 14 mA PSRR Offset Full 1 1 mV/V Gain Full 0.2 0.2 %/V POWER CONSUMPTION3 LVDS Outputs Full 1.7 1.8 1.9 2.2 W CMOS Outputs (DC Input) Full 1.5 1.7 W 1 Measured at the maximum clock rate, fIN = 15 MHz, full-scale sine wave, with a 100 Ω differential termination on each pair of output bits for LVDS output mode and approximately 5 pF loading on each output bit for CMOS output mode. 2 Input capacitance or resistance refers to the effective impedance between one differential input pin and AGND. Refer to Figure 6 for the equivalent analog input structure. 3 For SFDR = AVDD1, IAVDD2 power increases by ~70 mW for the AD9460BSVZ-80 and ~20 mW for the AD9460BSVZ-105. Rev. 0 | Page 3 of 32 Document Outline FEATURES FUNCTIONAL BLOCK DIAGRAM APPLICATIONS GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS EQUIVALENT CIRCUITS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION ANALOG INPUT AND REFERENCE OVERVIEW Internal Reference Connection Internal Reference Trim External Reference Operation Analog Inputs CLOCK INPUT CONSIDERATIONS Jitter Considerations POWER CONSIDERATIONS DIGITAL OUTPUTS LVDS Mode CMOS Mode TIMING OPERATIONAL MODE SELECTION Data Format Select Output Mode Select Duty Cycle Stabilizer SFDR Enhancement EVALUATION BOARD OUTLINE DIMENSIONS ORDERING GUIDE
