Datasheet AD9461 (Analog Devices) - 7

AD9461 TIMING DIAGRAMS N – 1 N + 15 N N + 14 AIN N + 1 N + 13 tCLKL tCLKH 1/fS CLK+ CLK– tPD N – 13 N – 12 N N + 1 DATA OUT 13 CLOCK CYCLES DCO+ DCO–
02 0
t
1-
CPD
01 06 Figure 2. LVDS Mode Timing Diagram
N N – 1 N + 1 VIN N + 2 tCLKL tCLKH CLK– CLK+ tPD 13 CLOCK CYCLES DX N – 13 N – 12 N – 1 N DCO+
3
DCO–
-00 1 01 06 Figure 3. CMOS Timing Diagram Rev. 0 | Page 6 of 28 Document Outline FEATURES FUNCTIONAL BLOCK DIAGRAM APPLICATIONS GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS EQUIVALENT CIRCUITS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION ANALOG INPUT AND REFERENCE OVERVIEW Internal Reference Connection Internal Reference Trim External Reference Operation Analog Inputs CLOCK INPUT CONSIDERATIONS Jitter Considerations POWER CONSIDERATIONS DIGITAL OUTPUTS LVDS Mode CMOS Mode TIMING OPERATIONAL MODE SELECTION Data Format Select Output Mode Select Duty Cycle Stabilizer SFDR Enhancement EVALUATION BOARD OUTLINE DIMENSIONS ORDERING GUIDE