AD9246REVISION HISTORY Deleted Figure 52 ..16 8/06—Rev. 0 to Rev. A Changes to Figure 41 ..17 Added 80 MSPS .. Universal Changes to Figure 46 ..19 Changes to Features ..1 Inserted Figure 54 ...21 Deleted Figures 19, 20, 22, 23 ..11 Added Data Clock Output (DCO) Section ...22 Deleted Figures 24, 25, 27 to 29...12 Changes to Table 15 ..25 Deleted Figures 31, 34...13 Changes to Table 16 ..39 Deleted Figures 37, 38, 40, 41 ..14 Changes to the Ordering Guide ..42 Deleted Figure 46 ..15 4/06—Revision 0: Initial Version Rev. A | Page 3 of 44 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING DIAGRAM ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS EQUIVALENT CIRCUITS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION ANALOG INPUT CONSIDERATIONS VOLTAGE REFERENCE CLOCK INPUT CONSIDERATIONS JITTER CONSIDERATIONS POWER DISSIPATION AND STANDBY MODE DIGITAL OUTPUTS TIMING SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI MEMORY MAP READING THE MEMORY MAP REGISTER TABLE MEMORY MAP REGISTER TABLE LAYOUT CONSIDERATIONS POWER AND GROUND RECOMMENDATIONS CML RBIAS REFERENCE DECOUPLING EVALUATION BOARD POWER SUPPLIES INPUT SIGNALS OUTPUT SIGNALS DEFAULT OPERATION AND JUMPER SELECTION SETTINGS ALTERNATIVE CLOCK CONFIGURATIONS ALTERNATIVE ANALOG INPUT DRIVE CONFIGURATION SCHEMATICS EVALUATION BOARD LAYOUTS BILL OF MATERIALS OUTLINE DIMENSIONS ORDERING GUIDE
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