Datasheet AD9445 (Analog Devices) - 9

AD9445 ABSOLUTE MAXIMUM RATINGS Table 5.
Stresses above those listed under Absolute Maximum Ratings
With
may cause permanent damage to the device. This is a stress
Respect Parameter To Rating
rating only; functional operation of the device at these or any ELECTRICAL other conditions above those indicated in the operational AVDD1 AGND −0.3 V to +4 V section of this specification is not implied. Exposure to absolute AVDD2 AGND −0.3 V to +6 V maximum rating conditions for extended periods may affect DRVDD DGND −0.3 V to +4 V device reliability. AGND DGND −0.3 V to +0.3 V
THERMAL RESISTANCE
AVDD1 DRVDD −4 V to +4 V The heat sink of the AD9445 package must be soldered to ground. AVDD2 DRVDD −4 V to +6 V AVDD2 AVDD1 −4 V to +6 V
Table 6.
D0± to D13± DGND –0.3 V to DRVDD + 0.3 V
Package Type θJA θJB θJC Unit
CLK+/CLK− AGND –0.3 V to AVDD1 + 0.3 V 100-lead TQFP/EP 19.8 8.3 2 °C/W OUTPUT MODE, DCS AGND –0.3 V to AVDD1 + 0.3 V MODE, DFS, SFDR, RF ENABLE Typical θJA = 19.8°C/W (heat sink soldered) for multilayer board in still air. VIN+, VIN− AGND –0.3 V to AVDD2 + 0.3 V VREF AGND –0.3 V to AVDD1 + 0.3 V Typical θJB = 8.3°C/W (heat sink soldered) for multilayer board SENSE AGND –0.3 V to AVDD1 + 0.3 V in still air. REFT, REFB AGND –0.3 V to AVDD1 + 0.3 V ENVIRONMENTAL Typical θJC = 2°C/W (junction to exposed heat sink) represents Storage Temperature –65°C to +125°C the thermal resistance through heat sink path. Range Airflow increases heat dissipation, effectively reducing θJA. Also, Operating Temperature –40°C to +85°C Range more metal directly in contact with the package leads from Lead Temperature 300°C metal traces through holes, ground, and power planes reduces (Soldering 10 sec) the θJA. It is required that the exposed heat sink be soldered to Junction Temperature 150°C the ground plane.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. 0 | Page 8 of 40 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION TERMINOLOGY PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS EQUIVALENT CIRCUITS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION ANALOG INPUT AND REFERENCE OVERVIEW Internal Reference Connection Internal Reference Trim External Reference Operation Analog Inputs High IF Applications CLOCK INPUT CONSIDERATIONS Jitter Considerations POWER CONSIDERATIONS DIGITAL OUTPUTS LVDS Mode CMOS Mode TIMING OPERATIONAL MODE SELECTION Data Format Select Output Mode Select Duty Cycle Stabilizer RF ENABLE EVALUATION BOARD OUTLINE DIMENSIONS ORDERING GUIDE