Datasheet AD7276, AD7277, AD7278 (Analog Devices) - 9

Data Sheet AD7276/AD7277/AD7278 t4 t8 SCLK SCLK VIH
002
SDATA 1.4V
004
SDATA VIL
04903- 04903- Figure 2. Access Time After SCLK Falling Edge Figure 4. SCLK Falling Edge SDATA Three-State
t7 SCLK VIH
003
SDATA VIL
04903- Figure 3. Hold Time After SCLK Falling Edge Rev. D | Page 9 of 28 Document Outline FEATURES GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS AD7276 SPECIFICATIONS AD7277 SPECIFICATIONS AD7278 SPECIFICATIONS TIMING SPECIFICATIONS—AD7276/AD7277/AD7278 TIMING EXAMPLES Timing Example 1 Timing Example 2 ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CIRCUIT INFORMATION CONVERTER OPERATION ADC TRANSFER FUNCTION TYPICAL CONNECTION DIAGRAM Analog Input Digital Inputs MODES OF OPERATION Normal Mode Partial Power-Down Mode Full Power-Down Mode Power-Up Times POWER VS. THROUGHPUT RATE SERIAL INTERFACE AD7278 IN A 10 SCLK CYCLE SERIAL INTERFACE MICROPROCESSOR INTERFACING AD7276/AD7277/AD7278 to Blackfin Processor APPLICATION HINTS GROUNDING AND LAYOUT EVALUATING PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE NOTES