Datasheet AD7798, AD7799 (Analog Devices) - 18

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AD7798/AD7799 Data Sheet ADC CIRCUIT INFORMATION AVDD GND AVDD REFERENCE DETECT REFIN(+) AD7798/AD7799 IN+ OUT– OUT+ AIN1(+) AVDD AIN1(–) IN– DOUT/RDY AIN2(+) SERIAL MUX INTERFACE DIN Σ-Δ IN-AMP AND ADC SCLK AIN2(–) CONTROL LOGIC CS REFIN(–) GND DVDD INTERNAL PSW CLOCK
012 04856- Figure 11. Basic Connection Diagram
OVERVIEW 0
The AD7798/AD7799 are low power ADCs that each incorporate a ∑-∆ modulator, a buffer, an in-amp, and on-chip digital filtering
–20
intended for the measurement of wide dynamic range, low frequency signals, such as those in pressure transducers and
–40
weigh scales.
(dB)
Each part has three differential inputs that can be buffered or
–60
unbuffered. The reference is provided by an external reference source. Figure 11 shows the basic connections required to
–80
operate the parts. The output rate of the AD7798/AD7799 (fADC) is user-program-
–100
04856-013 mable. The al owable update rates, along with the corresponding
0 20 40 60 80 100 120
settling times, are listed in Table 14. Normal mode rejection is
FREQUENCY (Hz)
Figure 12. Filter Profile with Update Rate = 4.17 Hz the major function of the digital filter. Simultaneous 50 Hz and 60 Hz rejection is optimized when the update rate equals 16.7 Hz or less, because notches are placed at both 50 Hz and 60 Hz with
0
these update rates (see Figure 13). The AD7798/AD7799 use slightly different filter types,
–20
depending on the output update rate, so that the rejection of quantization noise and device noise is optimized. When the
–40
update rate ranges from 4.17 Hz to 12.5 Hz, a sinc3 filter, along with an averaging filter, is used. When the update rate ranges
(dB)
from 16.7 Hz to 39 Hz, a modified sinc3 filter is used. This filter
–60
gives simultaneous 50 Hz and 60 Hz rejection when the update rate equals 16.7 Hz. A sinc4 filter is used when the update rate
–80
ranges from 50 Hz to 242 Hz. Final y, an integrate-only filter is used when the update rate equals 470 Hz. Figure 12 through 04856-014 Figure 15 show the frequency responses of the different filter
–100 0 20 40 60 80 100 120 140 160 180 200
types for a few of the update rates.
FREQUENCY (Hz)
Figure 13. Filter Profile with Update Rate = 16.7 Hz Rev. B | Page 18 of 28 Document Outline Features Interface Applications Functional Block Diagram General Description Revision History Specifications Timing Characteristics Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Output Noise and Resolution Specifications AD7798 AD7799 Typical Performance Characteristics On-Chip Registers Communication Register RS2, RS1, RS0 = 0, 0, 0 Status Register RS2, RS1, RS0 = 0, 0, 0; Power-On/Reset = 0x80 (AD7798)/0x88 (AD7799) Mode Register RS2, RS1, RS0 = 0, 0, 1; Power-On/Reset = 0x000A Configuration Register RS2, RS1, RS0 = 0, 1, 0; Power-On/Reset = 0x0710 Data Register RS2, RS1, RS0 = 0, 1, 1; Power-On/Reset = 0x0000(00) ID Register RS2, RS1, RS0 = 1, 0, 0; Power-On/Reset = 0xX8 (AD7798)/0xX9 (AD7799) IO Register RS2, RS1, RS0 = 1, 0, 1; Power-On/Reset = 0x00 Offset Register RS2, RS1, RS0 = 1, 1, 0; Power-On/Reset = 0x8000(AD7798)/0x800000 (AD7799) Full-Scale Register RS2, RS1, RS0 = 1, 1, 1; Power-On/Reset = 0x5XXX (AD7798)/0x5XXX00 (AD7799) ADC Circuit Information Overview Digital Interface Single-Conversion Mode Continuous-Conversion Mode Continuous Read Circuit Description Analog Input Channel Instrumentation Amplifier Bipolar/Unipolar Configuration Data Output Coding Burnout Currents Reference Reference Detect Reset AVDD Monitor Calibration Grounding and Layout Applications Information Weigh Scales Outline Dimensions Ordering Guide