Datasheet AD9481 (Analog Devices) - 8

AD9481 TIMING DIAGRAM N–1 N+9 tA N N+8 N+10 VIN N+1 N+7 8 CYCLES tEH tEL 1/fS CLK+ CLK– tHDS DS+ DS– tSDS tV INTERLEAVED DATA OUT tPD PORT A STATIC INVALID N D7A TO D0A PORT B STATIC INVALID INVALID N+1 D7B TO D0B tSKA t t SKB CPD DCO+ STATIC DCO–
05045-002 Figure 2. Timing Diagram Rev. 0 | Page 7 of 28 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS DC SPECIFICATIONS DIGITAL SPECIFICATIONS AC SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING DIAGRAM ABSOLUTE MAXIMUM RATINGS EXPLANATION OF TEST LEVELS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TERMINOLOGY TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS APPLICATIONS ANALOG INPUTS VOLTAGE REFERENCE Fixed Reference External Reference Programmable Reference CLOCKING THE AD9481 DS INPUTS DIGITAL OUTPUTS INTERLEAVING TWO AD9481s DATA CLOCK OUT POWER-DOWN INPUT AD9481 EVALUATION BOARD POWER CONNECTOR ANALOG INPUTS GAIN OPTIONAL OPERATIONAL AMPLIFIER CLOCK OPTIONAL CLOCK BUFFER DS OPTIONAL XTAL VOLTAGE REFERENCE DATA OUTPUTS EVALUATION BOARD BILL OF MATERIALS (BOM) PCB SCHEMATICS PCB LAYERS OUTLINE DIMENSIONS ORDERING GUIDE