Datasheet AD9444 (Analog Devices) - 9

AD9444 ABSOLUTE MAXIMUM RATINGS Table 5. Thermal Resistance With
The heat sink of the AD9444 package must be soldered to
Parameter Respect to Min Max Unit
ground.
ELECTRICAL Table 6.
AVDD1 AGND −0.3 +4 V AVDD2 AGND −0.3 +6 V
Package Type θJA θJB θJC Unit
DRVDD DGND −0.3 +4 V 100-Lead TQFP/EP 19.8 8.3 2 °C/W AGND DGND −0.3 +0.3 V AVDD1 DRVDD −4 +4 V AVDD2 DRVDD −4 +6 V Typical θJA = 19.8°C/W (heat-sink soldered) for multilayer AVDD2 AVDD1 −4 +6 V board in still air. D0 to D13 DGND –0.3 DRVDD + 0.3 V Typical θJB = 8.3°C/W (heat-sink soldered) for multilayer board CLK, MODE AGND –0.3 AVDD1 + 0.3 V in still air. VIN+, VIN− AGND –0.3 AVDD2 + 0.3 V VREF AGND –0.3 AVDD1 + 0.3 V Typical θJC = 2°C/W (junction to exposed heat sink) represents SENSE AGND –0.3 AVDD1 + 0.3 V the thermal resistance through heat-sink path. REFT, REFB AGND –0.3 AVDD1 + 0.3 V Airflow increases heat dissipation effectively reducing θ
ENVIRONMENTAL
JA. Also, more metal directly in contact with the package leads, from Storage Temperature –65 +125 °C metal traces, through holes, ground, and power planes, reduces Operating Temperature Range –40 +85 °C the θ Lead Temperature Range 300 °C JA. It is required that the exposed heat sink be soldered to (Soldering 10 sec) the ground plane. Junction Temperature 150 °C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprie- tary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. 0 | Page 8 of 40 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS EXPLANATION OF TEST LEVELS ABSOLUTE MAXIMUM RATINGS Thermal Resistance ESD CAUTION DEFINITIONS OF SPECIFICATIONS PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS EQUIVALENT CIRCUITS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION ANALOG INPUT AND REFERENCE OVERVIEW Internal Reference Connection Internal Reference Trim External Reference Operation Analog Inputs CLOCK INPUT CONSIDERATIONS Jitter Considerations POWER CONSIDERATIONS DIGITAL OUTPUTS LVDS Mode CMOS Mode TIMING OPERATIONAL MODE SELECTION Data Format Select Output Mode Select Duty Cycle Stabilizer EVALUATION BOARD LVDS EVALUATION BOARD SCHEMATICS LVDS MODE EVALUATION BOARD BILL OF MATERIALS (BOM) CMOS EVALUATION BOARD SCHEMATICS CMOS MODE EVALUATION BOARD BILL OF MATERIALS (BOM) OUTLINE DIMENSIONS ORDERING GUIDE