Datasheet AD9215 (Analog Devices) - 4

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Data Sheet AD9215 SPECIFICATIONS
AVDD = 3 V, DRVDD = 2.5 V, specified maximum conversion rate, 2 V p-p differential input, 1.0 V internal reference, unless otherwise noted.
Table 1. DC Specifications AD9215BRU-65/ AD9215BRU-80/ AD9215BRU-105/ AD9215BCP-65 AD9215BCP-80 AD9215BCP-105 Test Parameter Temp Level Min Typ Max Min Typ Max Min Typ Max Unit
RESOLUTION Full VI 10 10 10 Bits ACCURACY No Missing Codes Full VI Guaranteed Guaranteed Guaranteed Offset Error1 Full VI ±0.3 ±2.0 ±0.3 ±2.0 ±0.3 ±2.0 % FSR Gain Error1 Full VI 0 +1.5 +4.0 +1.5 +4.0 +1.5 +4.0 % FSR Differential Nonlinearity (DNL)2 Full VI −1.0 ±0.5 +1.0 −1.0 ±0.5 +1.0 −1.0 ±0.6 +1.2 LSB Integral Nonlinearity (INL)2 Full VI ±0.5 ±1.2 ±0.5 ±1.2 ±0.65 ±1.2 LSB TEMPERATURE DRIFT Offset Error1 Full V +15 +15 +15 ppm/°C Gain Error1 Full V +30 +30 +30 ppm/°C Reference Voltage (1 V Mode) Full V ±230 ±230 ±230 ppm/°C INTERNAL VOLTAGE REFERENCE Output Voltage Error (1 V Mode) Full VI ±2 ±35 ±2 ±35 ±2 ±35 mV Load Regulation @ 1.0 mA Full V 0.2 0.2 0.2 mV Output Voltage Error (0.5 V Mode) Full V ± 1 ±1 ±1 mV Load Regulation @ 0.5 mA Full V 0.2 0.2 0.2 mV INPUT REFERRED NOISE VREF = 0.5 V 25°C V 0.8 0.8 0.8 LSB rms VREF = 1.0 V 25°C V 0.4 0.4 0.4 LSB rms ANALOG INPUT Input Span, VREF = 0.5 V Full IV 1 1 1 V p-p Input Span, VREF = 1.0 V Full IV 2 2 2 V p-p Input Capacitance3 Full V 2 2 2 pF REFERENCE INPUT RESISTANCE Full V 7 7 7 kΩ POWER SUPPLIES Supply Voltage AVDD Full IV 2.7 3.0 3.3 2.7 3.0 3.3 2.7 3.0 3.3 V DRVDD Full IV 2.25 2.5 3.6 2.25 2.5 3.6 2.25 2.5 3.6 V Supply Current I 2 AVDD Full VI 32 35 34.5 39 40 44 mA I 2 DRVDD 25°C V 7.0 8.6 11.3 mA PSRR Full V ± 0.1 ± 0.1 ± 0.1 % FSR POWER CONSUMPTION Sine Wave Input2 I 2 AVDD Full VI 96 104 120 mW I 2 DRVDD 25°C V 18 20 25 mW Standby Power4 25°C V 1.0 1.0 1.0 mW 1 With a 1.0 V internal reference. 2 Measured at fIN = 2.4 MHz, full-scale sine wave, with approximately 5 pF loading on each output bit. 3 Input capacitance refers to the effective capacitance between one differential input pin and AGND. Refer to Figure 5 for the equivalent analog input structure. 4 Standby power is measured with a dc input, the CLK pin inactive (i.e., set to AVDD or AGND). Rev. B | Page 3 of 36 Document Outline Specifications Absolute Maximum Ratings1 Explanation of Test Levels ESD Caution Pin Configurations and Function Descriptions Equivalent Circuits Definitions of Specifications Aperture Delay Aperture Jitter Clock Pulse Width and Duty Cycle Differential Nonlinearity (DNL, No Missing Codes) Effective Number of Bits (ENOB) Gain Error Integral Nonlinearity (INL) Maximum Conversion Rate Minimum Conversion Rate Offset Error Out-of-Range Recovery Time Output Propagation Delay Power Supply Rejection Signal-to-Noise and Distortion (SINAD) Ratio Signal-to-Noise Ratio (SNR) Spurious-Free Dynamic Range (SFDR) Temperature Drift Total Harmonic Distortion (THD) Two-Tone SFDR Typical Performance Characteristics Applying the AD9215 Theory of Operation Analog Input and Reference Overview Differential Input Configurations Single-Ended Input Configuration Clock Input and Considerations Power Dissipation and Standby Mode Digital Outputs Timing Voltage Reference Internal Reference Connection External Reference Operation Operational Mode Selection Evaluation Board Outline Dimensions Ordering Guide