link to page 7 link to page 7 link to page 7 link to page 7 link to page 7 link to page 15 AD9238DIGITAL SPECIFICATIONS AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, CLK_A = CLK_B; AIN = −0.5 dBFS differential input, 1.0 V internal reference, TMIN to TMAX, DCS enabled, unless otherwise noted. Table 3.TestAD9238BST/BCP-20AD9238BST/BCP-40AD9238BST/BCP-65ParameterTempLevelMinTypMaxMinTypMaxMinTypMaxUnit LOGIC INPUTS High Level Input Voltage Full IV 2.0 2.0 2.0 V Low Level Input Voltage Full IV 0.8 0.8 0.8 V High Level Input Current Full IV −10 +10 −10 +10 −10 +10 μA Low Level Input Current Full IV −10 +10 −10 +10 −10 +10 μA Input Capacitance Full IV 2 2 2 pF LOGIC OUTPUTS1 High Level Output Voltage Full IV DRVDD − DRVDD − DRVDD − V 0.05 0.05 0.05 Low Level Output Voltage Full IV 0.05 0.05 0.05 V 1 Output voltage levels measured with capacitive load only on each output. SWITCHING SPECIFICATIONS AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, CLK_A = CLK_B; AIN = −0.5 dBFS differential input, 1.0 V internal reference, TMIN to TMAX, DCS enabled, unless otherwise noted. Table 4.TestAD9238BST/BCP-20AD9238BST/BCP-40AD9238BST/BCP-65ParameterTempLevelMinTypMaxMinTypMaxMinTypMaxUnit SWITCHING PERFORMANCE Maximum Conversion Rate Full VI 20 40 65 MSPS Minimum Conversion Rate Full V 1 1 1 MSPS CLK Period Full V 50.0 25.0 15.4 ns CLK Pulse-Width High1 Full V 15.0 8.8 6.2 ns CLK Pulse-Width Low1 Full V 15.0 8.8 6.2 ns DATA OUTPUT PARAMETER Output Delay2 (tPD) Full VI 2 3.5 6 2 3.5 6 2 3.5 6 ns Pipeline Delay (Latency) Full V 7 7 7 Cycles Aperture Delay (tA) Full V 1.0 1.0 1.0 ns Aperture Uncertainty (tJ) Full V 0.5 0.5 0.5 ps rms Wake-Up Time3 Full V 2.5 2.5 2.5 ms OUT-OF-RANGE RECOVERY TIME Full V 2 2 2 Cycles 1 The AD9238-65 model has a duty cycle stabilizer circuit that, when enabled, corrects for a wide range of duty cycles (see Figure 24). 2 Output delay is measured from clock 50% transition to data 50% transition, with a 5 pF load on each output. 3 Wake-up time is dependent on the value of the decoupling capacitors; typical values shown with 0.1 μF and 10 μF capacitors on REFT and REFB. NN+1N+2N+8N–1N+3ANALOGN+7N+4INPUTN+5N+6CLOCKDATAN–9N–8N–7N–6N–5N–4N–3N–2N–1NOUTtMIN 2.0ns,PD = MAX 6.0ns 02640-002 Figure 2. Timing Diagram Rev. C | Page 6 of 48 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS EXPLANATION OF TEST LEVELS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TERMINOLOGY TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS THEORY OF OPERATION ANALOG INPUT Differential Input Configurations Single-Ended Input Configuration CLOCK INPUT AND CONSIDERATIONS POWER DISSIPATION AND STANDBY MODE DIGITAL OUTPUTS TIMING DATA FORMAT VOLTAGE REFERENCE Internal Reference Connection External Reference Operation AD9238 LQFP EVALUATION BOARD CLOCK CIRCUITRY ANALOG INPUTS REFERENCE CIRCUITRY DIGITAL CONTROL LOGIC OUTPUTS LQFP EVALUATION BOARD BILL OF MATERIALS (BOM) LQFP EVALUATION BOARD SCHEMATICS LQFP PCB LAYERS DUAL ADC LFCSP PCB POWER CONNECTOR ANALOG INPUTS OPTIONAL OPERATIONAL AMPLIFIER CLOCK VOLTAGE REFERENCE DATA OUTPUTS LFCSP EVALUATION BOARD BILL OF MATERIALS (BOM) LFCSP PCB SCHEMATICS LFCSP PCB LAYERS THERMAL CONSIDERATIONS OUTLINE DIMENSIONS ORDERING GUIDE
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