Datasheet AD7650 (Analog Devices) - 4

AD7650 AD7650 Parameter Condition Min Typ Max Unit
POWER SUPPLIES (continued) Operating Current5 570 kSPS Throughput AVDD 15.5 mA DVDD6 4.2 mA OVDD6 100 µA Power Dissipation6 570 kSPS Throughput5 115 mW 444 kSPS Throughput7 77 mW 100 SPS Throughput7 21 µW In Power-Down Mode8 7 µW TEMPERATURE RANGE9 Specified Performance TMIN to TMAX –40 +85 °C NOTES 1LSB means Least Significant Bit. With the 0 V to 2.5 V input range, one LSB is 38.15 µV. 2See Definition of Specifications section. These specifications do not include the error contribution from the external reference. 3Tested in warp mode. 4All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full-scale unless otherwise specified. 5In warp mode. 6Tested in parallel reading mode. 7In impulse mode. 8With all digital inputs forced to OVDD or OGND respectively. 9Contact factory for extended temperature range. Specifications subject to change without notice.
TIMING SPECIFICATIONS (–40
ⴗ
C to +85
ⴗ
C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.) Parameter Symbol Min Typ Max Unit
REFER TO FIGURES 8 AND 9 Convert Pulsewidth t1 5 ns Time Between Conversions t2 1.75/2/2.25 Note 1 µs (Warp Mode/Normal Mode/Impulse Mode) CNVST LOW to BUSY HIGH Delay t3 30 ns BUSY HIGH All Modes Except in t4 1.5/1.75/2 µs Master Serial Read After Convert Mode (Warp Mode/Normal Mode/Impulse Mode) Aperture Delay t5 2 ns End of Conversion to BUSY LOW Delay t6 10 ns Conversion Time t7 1.5/1.75/2 µs (Warp Mode/Normal Mode/Impulse Mode) Acquisition Time t8 250 ns RESET Pulsewidth t9 10 ns REFER TO FIGURES 10, 11 AND 12 (Parallel Interface Modes) CNVST LOW to DATA Valid Delay t10 1.5/1.75/2 µs (Warp Mode/Normal Mode/Impulse Mode) DATA Valid to BUSY LOW Delay t11 45 ns Bus Access Request to DATA Valid t12 40 ns Bus Relinquish Time t13 5 15 ns REFER TO FIGURES 13 AND 14 (Master Serial Interface Modes)2 CS LOW to SYNC Valid Delay t14 10 ns CS LOW to Internal SCLK Valid Delay2 t15 10 ns CS LOW to SDOUT Delay t16 10 ns CNVST LOW to SYNC Delay t17 25/275/525 ns (Warp Mode/Normal Mode/Impulse Mode) SYNC Asserted to SCLK First Edge Delay t18 4 ns Internal SCLK Period t19 40 75 ns Internal SCLK HIGH (INVSCLK Low)3 t20 30 ns Internal SCLK LOW (INVSCLK Low)3 t21 9.5 ns SDOUT Valid Setup Time t22 4.5 ns SDOUT Valid Hold Time t23 3 ns REV. 0 –3–