Datasheet AD7709 (Analog Devices) - 7

AD7709 (V TIMING CHARACTERISTICS1, 2 DD = 2.7 V to 3.6 V or VDD = 4.75 V to 5.25 V; GND = 0 V; XTAL = 32.768 kHz; Input Logic 0 = 0 V, Logic 1 = VDD unless otherwise noted.) Limit at TMIN, TMAX Parameter (A, B Version) Unit Conditions/Comments
t1 30.5176 ms typ Crystal Oscillator Period t2 50 ns min RESET Pulsewidth Read Operation t3 0 ns min RDY to CS Setup Time t4 0 ns min CS Falling Edge to SCLK Active Edge Setup Time3 t 4 5 0 ns min SCLK Active Edge to Data Valid Delay3 60 ns max VDD = 4.75 V to 5.25 V 80 ns max VDD = 2.7 V to 3.6 V t 4, 5 5A 0 ns min CS Falling Edge to Data Valid Delay 60 ns max VDD = 4.75 V to 5.25 V 80 ns max VDD = 2.7 V to 3.6 V t6 100 ns min SCLK High Pulsewidth t7 100 ns min SCLK Low Pulsewidth t8 0 ns min CS Rising Edge to SCLK Inactive Edge Hold Time3 t 6 9 10 ns min Bus Relinquish Time after SCLK Inactive Edge3 80 ns max t10 100 ns max SCLK Active Edge to RDY High3, 7 Write Operation t11 0 ns min CS Falling Edge to SCLK Active Edge Setup Time3 t12 30 ns min Data Valid to SCLK Edge Setup Time t13 25 ns min Data Valid to SCLK Edge Hold Time t14 100 ns min SCLK High Pulsewidth t15 100 ns min SCLK Low Pulsewidth t16 0 ns min CS Rising Edge to SCLK Edge Hold Time NOTES 1 Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. 2 See Figures 2 and 3. 3 SCLK active edge is falling edge of SCLK. 4 These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross the VOL or VOH limits. 5 This specification comes into play only if CS goes low while SCLK is low. It is required primarily for interfacing to DSP machines. 6 These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapo- lated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the Timing Characteristics table are the true bus relinquish times of the part and as such are independent of external bus loading capacitances. 7 RDY returns high after a read of the ADC. The same data can be read again, if required, while RDY is high, although care should be taken that subsequent reads do not occur close to the next output update. –6– REV. A Document Outline FEATURES INTERFACE POWER ON-CHIP FUNCTIONS APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS SPECIFICATIONS TIMING CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION ORDERING GUIDE PIN FUNCTION DESCRIPTIONS Typical Performance Characteristics ADC CIRCUIT INFORMATION Overview Sigma-Delta ADC NOISE PERFORMANCE ON-CHIP REGISTERS Communications Register (A1, A0 = 0, 0) Status Register (A1, A0 = 0, 0; Power-On-Reset = 00H) Configuration Register (A1, A0 = 0, 1; Power-On-Reset = 000007H) Filter Register (A1, A0 = 1, 0; Power-On-Reset = 45h) ADC Data Result Register (A1, A0 = 1, 1; Power-On-Reset = 0000h CONFIGURING THE AD7709 DIGITAL INTERFACE MICROCOMPUTER/MICROPROCESSOR INTERFACING AD7709-to-68HC11 Interface AD7709-to-8051 Interface AD7709-to-ADSP-2103/ADSP-2105 Interface CIRCUIT DESCRIPTION Analog Input Channels Programmable Gain Amplifier Bipolar/Unipolar Configuration Data Output Coding Excitation Currents Crystal Oscillator Reference Input Reset Input Power-Down Mode Grounding and Layout APPLICATIONS Pressure Measurement Temperature Measurement 3-Wire RTD Configurations Smart Transmitters OUTLINE DIMENSIONS Revision History