Datasheet AD7671 (Analog Devices) - 10

Typical Performance Characteristics–AD7671 2.5 60 2.0 50 1.5 1.0 40 0.5 0 30 INL – LSB –0.5 20 –1.0 NUMBER OF UNITS –1.5 10 –2.0 –2.5 0 0 16384 32768 49152 65536 –3.0 –2.7 –2.4 –2.1 –1.8 –1.5 –1.2 –0.9 –0.6 –0.3 CODE NEGATIVE INL – LSB
TPC 1. Integral Nonlinearity vs. Code TPC 4. Typical Negative INL Distribution (314 Units)
1.75 8000 1.50 7029 7039 7000 1.25 6000 1.00 0.75 5000 0.50 4000 0.25 COUNTS DNL – LSB 0 3000 –0.25 2000 –0.50 1297 986 1000 –0.75 0 0 17 25 0 0 –1.00 0 0 16384 32768 49152 65536 7FFD 7FFE 7FFF 8000 8001 8002 8003 8004 8005 8005 CODE CODE IN HEXA
TPC 2. Differential Nonlinearity vs. Code TPC 5. Histogram of 16,384 Conversions of a DC Input at the Code Transition
60 10000 9503 9000 50 8000 7000 40 6000 30 5000 COUNTS 4000 3296 3344 NUMBER OF UNITS 20 3000 2000 10 1000 0 0 2 132 106 1 0 0 0 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 7FFC 7FFD 7FFE 7FFF 8000 8001 8002 8003 8004 8005 8006 POSITIVE INL – LSB CODE IN HEXA
TPC 3. Typical Positive INL Distribution (314 Units) TPC 6. Histogram of 16,384 Conversions of a DC Input at the Code Center REV. C –9– Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PulSAR Selection PRODUCT HIGHLIGHTS SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION ORDERING GUIDE PIN FUNCTION DESCRIPTION DEFINITION OF SPECIFICATIONS Integral Nonlinearity Error (INL) Differential Nonlinearity Error (DNL) Full-Scale Error Bipolar Zero Error Unipolar Zero Error Spurious-Free Dynamic Range (SFDR) Effective Number of Bits (ENOB) Total Harmonic Distortion (THD) Signal-to-Noise Ratio (SNR) Signal-to-(Noise + Distortion) Ratio (S/[N+D]) Aperture Delay Transient Response Typical Performance Characteristics CIRCUIT INFORMATION CONVERTER OPERATION Modes of Operation Transfer Functions TYPICAL CONNECTION DIAGRAM Analog Inputs Driver Amplifier Choice Voltage Reference Input Scaler Reference Input (Bipolar Input Ranges) Power Supply POWER DISSIPATION CONVERSION CONTROL DIGITAL INTERFACE PARALLEL INTERFACE SERIAL INTERFACE SLAVE SERIAL INTERFACE External Clock MASTER SERIAL INTERFACE Internal Clock External Discontinuous Clock Data Read after Conversion External Clock Data Read during Conversion MICROPROCESSOR INTERFACING SPI Interface (MC68HC11) ADSP-21065L in Master Serial Interface APPLICATION HINTS Layout Evaluating the AD7671 Performance OUTLINE DIMENSIONS Revision History