Datasheet AD9410 (Analog Devices) - 7

AD9410 SAMPLE N+3 SAMPLE N–1 SAMPLE N SAMPLE N+4 SAMPLE N+5 AIN tA SAMPLE N–2 SAMPLE N+1 SAMPLE N+2 SAMPLE N+6 tEH tEL 1/fS CLK+ CLK– tSDS tHDS DS DS tPD tV INTERLEAVED DATA OUT PORT A STATIC INVALID INVALID INVALID DATA N+1 DATA N+3 D7 TO D0 PORT B STATIC INVALID INVALID INVALID DATA N DATA N+2 D7 TO D0 PARALLEL DATA OUT PORT A STATIC INVALID INVALID INVALID INVALID DATA N+1 D7 TO D0 PORT B STATIC INVALID INVALID INVALID DATA N DATA N+2 D7 TO D0 tCPD DCO
2 00
STATIC
9- 67
DCO
01 Figure 2. Timing Diagram Rev. A | Page 6 of 20 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS SWITCHING SPECIFICATIONS DIGITAL SPECIFICATIONS AC SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS EXPLAINATION OF TEST LEVELS Test Level ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TERMINOLOGY EQUIVALENT CIRCUITS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION USING THE AD9410 Clock Input ANALOG INPUT DIGITAL OUTPUTS CLOCK OUTPUTS (DCO, ) VOLTAGE REFERENCE TIMING DATA SYNC (DS) OUTLINE DIMENSIONS ORDERING GUIDE