Datasheet AD9226 (Analog Devices) - 4

AD9226 DIGITAL SPECIFICATIONS (AVDD = 5 V, DRVDD = 3 V, fSAMPLE = 65 MSPS, VREF = 2.0 V, TMIN to TMAX, unless otherwise noted.) Parameters Temp Test Level Min Typ Max Unit
LOGIC INPUTS (Clock, DFS1, Duty Cycle1, and Output Enable1) High-Level Input Voltage Full IV 2.4 V Low-Level Input Voltage Full IV 0.8 V High-Level Input Current (VIN = AVDD) Full IV –10 +10 µA Low-Level Input Current (VIN = 0 V) Full IV –10 +10 µA Input Capacitance Full V 5 pF Output Enable1 Full IV DRVDD DRVDD V – 0 5 . + 0 5 . 2 2 LOGIC OUTPUTS (With DRVDD = 5 V) High-Level Output Voltage (IOH = 50 µA) Full IV 4.5 V High-Level Output Voltage (IOH = 0.5 mA) Full IV 2.4 V Low-Level Output Voltage (IOL = 1.6 mA) Full IV 0.4 V Low-Level Output Voltage (IOL = 50 µA) Full IV 0.1 V Output Capacitance 5 pF LOGIC OUTPUTS (With DRVDD = 3 V) High-Level Output Voltage (IOH = 50 µA) Full IV 2.95 V High-Level Output Voltage (IOH = 0.5 mA) Full IV 2.80 V Low-Level Output Voltage (IOL = 1.6 mA) Full IV 0.4 V Low-Level Output Voltage (IOL = 50 µA) Full IV 0.05 V NOTES 1LQFP package. Specifications subject to change without notice.
SWITCHING SPECIFICATIONS (TMIN to TMAX with AVDD = 5 V, DRVDD = 3 V, CL = 20 pF) Parameters Temp Test Level Min Typ Max Unit
Max Conversion Rate Full VI 65 MHz Clock Period1 Full V 15.38 ns CLOCK Pulsewidth High2 Full V 3 ns CLOCK Pulsewidth Low2 Full V 3 ns Output Delay Full V 3.5 7 ns Pipeline Delay (Latency) Full V 7 Clock Cycles Output Enable Delay3 Full V 15 ns NOTES 1The clock period may be extended to 10 µs without degradation in specified performance @ 25°C. 2When MODE pin is tied to AVDD or grounded, the AD9226 SSOP is not affected by clock duty cycle. 3LQFP package. Specifications subject to change without notice.
n+2 n+1 n+3 n n+8 ANALOG n+4 INPUT n+7 n+5 n+6 CLOCK DATA n–8 n–7 n–6 n–5 n–4 n–3 n–2 n–1 n n+1 OUT TOD = 7.0 MAX 3.5 MIN
Figure 1. Timing Diagram REV. B –3–