Datasheet AD7664 (Analog Devices) - 10

AD7664 0 92 8192 POINT FFT –20 fS = 570kHz fIN = 45.5322kHz, –0.5dB –40 SNR = 90.1dB SINAD = 89.4dB SNR –60 THD = –97.1dB 90 SFDR = 97.5dB –80 S/(N+D) –100 –120 88 AMPLITUDE (dB of Full Scale) –140 –160 SNR (REFERRED TO FULL SCALE) – dB –180 86 0 57 114 171 228 285 –60 –50 –40 –30 –20 –10 0 FREQUENCY (kHz) INPUT LEVEL – dB
TPC 7. FFT Plot TPC 10. SNR and S/(N+D) vs. Input Level (Referred to Full Scale)
100 16.0 96 –96 95 15.5 93 –98 SNR 90 15.0 THD S/(N+D) 85 14.5 –100 ENOB 90 ENOB – Bits THD – dB SNR 80 14.0 SNR AND S/[N+D] – dB SNR AND S/(N+D) – dB 87 –102 75 13.5 70 13.0 84 –104 1 10 100 1000 –55 –35 –15 5 25 45 65 85 105 125 FREQUENCY – kHz TEMPERATURE – C
TPC 8. SNR, S/(N+D), and ENOB vs. Frequency TPC 11. SNR, S/(N+D), THD vs. Temperature
–60 110 100k AVDD, WARP/NORMAL –65 105 10k –70 100 A SFDR DVDD, WARP/NORMAL 1k –75 95 AVDD, IMPULSE 100 –80 90 DVDD, IMPULSE –85 85 10 SFDR – dB 80 , HARMONIC – dB –90 1 THD THD –95 75 SECOND HARMONIC 0.1 OVDD, ALL MODES –100 70 OPERATING CURRENTS – 0.01 –105 65 THIRD HARMONIC –110 60 0.001 1 10 100 1000 0.1 1 10 100 1k 10k 100k 1M FREQUENCY – kHz SAMPLING RATE – SPS
TPC 9. THD, Harmonics, and SFDR vs. Frequency TPC 12. Operating Currents vs. Sample Rate REV. F –9– Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ORDERING GUIDE PIN CONFIGURATION PIN FUNCTION DESCRIPTIONS DEFINITION OF SPECIFICATIONS Integral Nonlinearity Error (INL) Differential Nonlinearity Error (DNL) Full-Scale Error Unipolar Zero Error Spurious-Free Dynamic Range (SFDR) Effective Number of Bits (ENOB) Total Harmonic Distortion (THD) Signal-to-Noise Ratio (SNR) Signal to (Noise + Distortion) Ratio (S/[N+D]) Aperture Delay Transient Response Overvoltage Recovery Typical Performance Characteristics CIRCUIT INFORMATION CONVERTER OPERATION Modes of Operation Transfer Functions TYPICAL CONNECTION DIAGRAM Analog Input Driver Amplifier Choice Voltage Reference Input Power Supply POWER DISSIPATION VERSUS THROUGHPUT CONVERSION CONTROL DIGITAL INTERFACE PARALLEL INTERFACE SERIAL INTERFACE MASTER SERIAL INTERFACE Internal Clock SLAVE SERIAL INTERFACE External Clock External Discontinuous Clock Data Read after Conversion External Clock Data Read during Conversion MICROPROCESSOR INTERFACING SPI Interface (ADSP-219x) APPLICATION HINTS Bipolar and Wider Input Ranges Layout OUTLINE DIMENSIONS Revision History