Datasheet AD6644 (Analog Devices) - 7

AD6644 TIMING DIAGRAM tA N + 3 N AIN N + 1 N + 2 tENCH tENCL N + 4 tENC ENCODE, N N + 1 N + 2 N + 3 N + 4 ENCODE tE_FL t t E_RL E_DR tS_E tH_E D[13:0], OVR N – 3 N – 2 N – 1 N t t H_DR S_DR DRY
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0971 0 Figure 2. Timing Diagram Rev. D | Page 6 of 24 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION PRODUCT HIGHLIGHTS FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS AC SPECIFICATIONS TIMING DIAGRAM ABSOLUTE MAXIMUM RATINGS EXPLANATION OF TEST LEVELS Test Level THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS TERMINOLOGY THEORY OF OPERATION APPLYING THE AD6644 Encoding the AD6644 Analog Input Power Supplies Digital Outputs Layout Information Jitter Considerations EVALUATION BOARD OUTLINE DIMENSIONS ORDERING GUIDE