Datasheet AD9203 (Analog Devices) - 5

link to page 26
AD9203 Parameter Symbol Min Typ Max Unit Conditions
Two-Tone Intermodulation Distortion IMD 68 dB f = 44.49 MHz and 45.52 MHz Differential Phase DP 0.2 Degree NTSC 40 IRE Ramp Differential Gain DG 0.3 % DIGITAL INPUTS High Input Voltage VIH 2.0 V Low Input Voltage VIL 0.4 V Clock Pulse Width High 11.25 ns Clock Pulse Width Low 11.25 ns Clock Period2 25 ns DIGITAL OUTPUTS High-Z Leakage IOZ ± 5.0 µA Output = 0 to DRVDD Data Valid Delay tOD 5 ns CL= 20 pF Data Enable Delay tDEN 6 ns CL= 20 pF Data High-Z Delay tDHZ 6 ns CL= 20 pF LOGIC OUTPUT (with DRVDD = 3 V) High Level Output Voltage (IOH = 50 µA) VOH 2.95 V High Level Output Voltage (IOH = 0.5 mA) VOH 2.80 V Low Level Output Voltage (IOL= 1.6 mA) VOL 0.3 V Low Level Output Voltage (IOL= 50 µA) VOL 0.05 V 1 Differential Input (2 V p-p). 2 The AD9203 will convert at clock rates as low as 20 kHz.
N+1 N N+2 N–1 N+3 ANALOG INPUT N+6 N+4 N+5 CLOCK DATA N–7 N–6 N–5 N–4 N–3 N–2 N–1 N N+1 OUT TOD = 3ns MIN 7ns MAX (CLOAD = 20pF)
00573-002 Figure 2. Timing Diagram Rev. B | Page 4 of 28 Document Outline FEATURES GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TERMINOLOGY TYPICAL PERFORMANCE CHARACTERISTICS OPERATIONS THEORY OF OPERATION OPERATIONAL MODES INPUT AND REFERENCE OVERVIEW INTERNAL REFERENCE CONNECTION EXTERNAL REFERENCE OPERATION CLAMP OPERATION DRIVING THE ANALOG INPUT OP AMP SELECTION GUIDE DIFFERENTIAL MODE OF OPERATION POWER CONTROL INTERFACING TO 5 V SYSTEMS CLOCK INPUT AND CONSIDERATIONS DIGITAL INPUTS AND OUTPUTS APPLICATIONS DIRECT IF DOWN CONVERSION ULTRASOUND APPLICATIONS EVALUATION BOARD OUTLINE DIMENSIONS ORDERING GUIDE