Datasheet AD73360 (Analog Devices) - 24

AD73360 Cascade Operation
In Cascade Mode, each device must know the number of de- The AD73360 has been designed to support up to eight devices vices in the cascade to be able to output data at the correct in a cascade connected to a single serial port (see Figure 17). time. Control Register A contains a 3-bit field (DC0–2) that is The SPORT interface protocol has been designed so that device programmed by the DSP during the programming phase. The addressing is built into the packet of information sent to the default condition is that the field contains 000b, which is equiva- device. This allows the cascade to be formed with no extra hard- lent to a single device in cascade (see Table XVIII). However, ware overhead for control signals or addressing. A cascade can for cascade operation this field must contain a binary value that be formed in either of the two modes previously discussed. is one less than the number of devices in the cascade. With a number of AD73360s in cascade each device takes a turn to
TFS SDIFS
send an ADC result to the DSP. For example, in a cascade of
MCLK DT SDI
two devices the data will be output as Device 2-Channel 1,
ADSP-2181 AD73360
Device 1-Channel 1, Device 2-Channel 2, Device 1-Channel 2
SCLK SCLK SE DSP
etc. When the first device in the cascade has transmitted its
DR SDO DEVICE 1 RESET
channel data there is an additional SCLK period during which
RFS SDOFS
the last device asserts its SDOFS as it begins its transmission of the next channel. This will not cause a problem for most DSPs
FL0 FL1
as they count clock edges after a frame sync and hence the
SDIFS MCLK
extra bit will be ignored.
SDI AD73360
When multiple devices are connected in cascade there are also
SE SCLK
restrictions concerning which ADC channels can be powered
SDO DEVICE 2 RESET
up. In all cases the cascaded devices must all have the same
SDOFS
channels powered up (i.e., for a cascade of two devices requir- ing Channels 1 and 2 on Device 1 and Channel 5 on Device 2,
D0 Q0
Channels 1, 2 and 5 must be powered up on both devices to
74HC74
ensure correct operation). Figure 18 shows the timing se-
D1 Q1
quence for two devices in cascade.
CLK Table XVIII. Device Count Settings
Figure 17. Connection of Two AD73360s Cascaded to
DC2 DC1 DC0 Cascade Length
ADSP-2181 0 0 0 1 There may be some restrictions in cascade operation due to the 0 0 1 2 number of devices configured in the cascade and the serial clock 0 1 0 3 rate chosen. The formula below gives an indication of whether 0 1 1 4 the combination of sample rate, serial clock and number of 1 0 0 5 devices can be successfully cascaded. This assumes a directly 1 0 1 6 coupled frame sync arrangement as shown in Figure 12 and does 1 1 0 7 not take any interrupt latency into account. 1 1 1 8 1 6 × [((Device Count − 1) × 16) + 17 ≥ ] Connection of a cascade of devices to a DSP, as shown in f Figure 17, is no more complicated than connecting a single S SCLK device. Instead of connecting the SDO and SDOFS to the When using the indirectly coupled frame sync configuration in DSP’s Rx port, these are now daisy-chained to the SDI and cascaded operation it is necessary to be aware of the restrictions SDIFS of the next device in the cascade. The SDO and in sending control word data to all devices in the cascade. The SDOFS of the final device in the cascade are connected to the user should ensure that there is sufficient time for all the control DSP’s Rx port to complete the cascade. SE and RESET on all words to be sent between reading the last ADC sample and the devices are fed from the signals that were synchronized with start of the next sample period. the MCLK using the circuit of Figure 19. The SCLK from only one device need be connected to the DSP’s SCLK input(s) as all devices will be running at the same SCLK frequency and phase.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 1 2 3 4 5 6 7 8 DEVICE 2 - CHANNEL 1 DEVICE 1 - CHANNEL 1 DEVICE 2 - CHANNEL 2
Figure 18. Cascade Timing for a Two-Device Cascade REV. B –23–