Datasheet AD9288 (Analog Devices) - 6

AD9288 TIMING DIAGRAMS SAMPLE N SAMPLE N + 1 SAMPLE N + 5 AINA, AINB tA SAMPLE N + 2 SAMPLE N + 3 SAMPLE N + 4 tEH tEL 1/fs ENCODE A, B tPD tV D7A–D0A DATA N – 4 DATA N – 3 DATA N – 2 DATA N – 1 DATA N DATA N + 1 D7B–D0B DATA N – 4 DATA N – 3 DATA N – 2 DATA N – 1 DATA N DATA N + 1
00585-003 Figure 2. Normal Operation, Same Clock (S1 = 1, S2 = 0) Channel Timing
SAMPLE SAMPLE SAMPLE SAMPLE SAMPLE N N + 1 N + 2 N + 3 N + 4 AINA, AINB tA tEH tEL 1/fs ENCODE A tPD tV ENCODE B D7A–D0A DATA N – 8 DATA N – 6 DATA N – 4 DATA N – 2 DATA N DATA N + 2 D7B–D0B DATA N – 7 DATA N – 5 DATA N – 3 DATA N – 1 DATA N + 1 DATA N + 3
00585-004 Figure 3. Normal Operation with Two Clock Sources (S1 = 1, S2 = 0) Channel Timing Rev. C | Page 5 of 24 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS EXPLANATION OF TEST LEVELS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TEST CIRCUITS TERMINOLOGY THEORY OF OPERATION USING THE AD9288 ENCODE INPUT DIGITAL OUTPUTS ANALOG INPUT VOLTAGE REFERENCE TIMING USER-SELECTABLE OPTIONS AD9218/AD9288 CUSTOMER PCB BOM EVALUATION BOARD POWER CONNECTOR ANALOG INPUTS VOLTAGE REFERENCE CLOCKING DATA OUTPUTS DATA FORMAT/GAIN TIMING TROUBLESHOOTING OUTLINE DIMENSIONS ORDERING GUIDE