Datasheet AD7729 (Analog Devices) - 6

AD7729 TIMING DIAGRAMS t1 t3 t2 t1 MCLK t3 t5 *ASCLK t6 t4 t2 *ASCLK IS INDIVIDUALLY PROGRAMMABLE IN FREQUENCY (MCLK/4 SHOWN HERE).
Figure 2. Clock Timing Figure 4. ASCLK
100
m
A IOL t1 t3 t2 MCLK TO OUTPUT PIN +2.1V CL t8 15pF *BSCLK t9 100
m
A IOH t7 *BSCLK IS INDIVIDUALLY PROGRAMMABLE IN FREQUENCY
Figure 3. Load Circuit for Timing Specifications
(MCLK/4 SHOWN HERE).
Figure 5. BSCLK
ASE (I) ASCLK (O) THREE-STATE t10 t17 t16 ASDIFS (I) t11 t11 t10 ASDI (I) D9 D8 A1 A0 D9 D8 D7 t t 12 13 THREE-STATE ASDOFS (O) t14 THREE-STATE ASDO (O) D9 A2 A1 A0 D9 D8 t NOTE 15 I = INPUT, O = OUTPUT
Figure 6. Auxiliary Serial Port ASPORT
BSE (I) THREE-STATE BSCLK (O) t18 t25 t24 BSDIFS (I) t19 t19 t18 BSDI (I) D9 D8 A1 A0 D9 D8 D7 t t THREE-STATE 20 21 BSDOFS (O) t THREE-STATE 22 BSDO (O) D9 A2 A1 A0 D9 D8 t23 NOTE I = INPUT, O = OUTPUT
Figure 7. Baseband Serial Port BSPORT REV. 0 –5–