Datasheet AD7894 (Analog Devices) - 11

AD7894 AD7894 to ADSP-2101/5 Interface
The BUSY line from the AD7894 is connected to the MODA/ An interface circuit between the AD7894 and the ADSP-2101/5 IRQA input of the DSP56002/L002 so that an interrupt will be DSP processor is shown in Figure 8. In the interface shown, the generated at the end of conversion. This ensures that the read RFS1 output from the ADSP-2101/5s SPORT1 serial port is operation will take place after conversion is finished. used to gate the serial clock (SCLK1) of the ADSP-2101/5 before it is applied to the SCLK input of the AD7894. The RFS1 output is configured for active high operation. The BUSY
MODA/IRQA BUSY
line from the AD7894 is connected to the IRQ2 line of the ADSP-2101/5 so that at the end of conversion an interrupt is
DSP56002/L002 AD7894
generated telling the ADSP-2101/5 to initiate a read operation.
SCK SCLK
The interface ensures a noncontinuous clock for the AD7894’s serial clock input, with only 16 serial clock pulses provided and
SDR SDATA
the serial clock line of the AD7894 remaining low between data transfers. The SDATA line from the AD7894 is connected to the DR1 line of the ADSP-2101/5’s serial port. Figure 9. AD7894 to DSP56002/L002 Interface The timing relationship between the SCLK1 and RFS1 outputs of the ADSP-2101/5 are such that the delay between the rising
AD7894 PERFORMANCE
edge of the SCLK1 and the rising edge of an active high RFS1
Linearity
is up to 30␣ ns. There is also a requirement that data must be set The linearity of the AD7894 is determined by the on-chip up 10␣ ns prior to the falling edge of the SCLK1 to be read cor- 14-bit D/A converter. This is a segmented DAC which is laser rectly by the ADSP-2101/5. The data access time for the AD7894 trimmed for 14-bit integral linearity and differential linearity. is 60␣ ns (A, B versions) from the rising edge of its SCLK input. Typical relative accuracy numbers for the part are ± 1/2␣ LSB Assuming a 10␣ ns propagation delay through the external AND while the typical DNL errors are ± 1/3␣ LSB. gate, the high time of the SCLK1 output of the ADSP-2105
Noise
must be ≥ (30 + 60 + 10 + 10)␣ ns, i.e., ≥ 110 ns. This means In an A/D converter, noise exhibits itself as code uncertainty in that the serial clock frequency with which the interface of Figure dc applications and as the noise floor (in an FFT, for example) 8 can work is limited to 4.5␣ MHz. in ac applications. In a sampling A/D converter like the AD7894, Another alternative scheme is to configure the ADSP-2101/5 all information about the analog input appears in the baseband such that it accepts an external noncontinuous serial clock. In from dc to 1/2 the sampling frequency. The input bandwidth of this case, an external noncontinuous serial clock is provided that the track/hold exceeds the Nyquist bandwidth, so an antialiasing drives the serial clock inputs of both the ADSP-2101/5 and the filter should be used to remove unwanted signals above fS/2 in AD7894. In this scheme, the serial clock frequency is limited to the input signal in applications where such signals exist. the processor’s cycle rate, up to a maximum of 13.8 MHz. Figure 10 shows a histogram plot for 8192 conversions of a dc input using the AD7894. The analog input was set at the center of a code transition. It can be seen that almost all the codes
IRQ2 BUSY
appear in the one output bin indicating very good noise perfor-
RFS1
mance from the ADC.
AD7894 ADSP-2101/5 SCLK SCLK1 6000 DR1 SDATA 5000
Figure 8. AD7894 to ADSP-2101/5 Interface
4000 AD7894 to DSP56002/L002 Interface
Figure 9 shows an interface circuit between the AD7894 and the
3000 COUNTS
DSP56002/L002 DSP processor. The DSP56002/L002 is configured for normal-mode asynchronous operation with gated
2000
clock. It is also set up for a 16-bit word with SCK as gated clock output. In this mode, the DSP56002/L002 provides 16
1000
serial clock pulses to the AD7894 in a serial read operation. The DSP56002/L002 assumes valid data on the first falling
0 97 98 99 100 101 102 103
edge of SCK so the interface is simply three-wire as shown in
ADC CODE
Figure 9. Figure 10. Histogram of 8192 Conversions of a DC Input –10– REV. 0