Datasheet AD7810 (Analog Devices) - 4

AD7810 Timing Characteristics1, 2 (–40
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C to +105
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C, VREF = VDD, unless otherwise noted) Parameter VDD = 5 V
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10% VDD = 3 V
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10% Unit Conditions/Comments
t1 2.3 2.3 µs (max) Conversion Time Mode 1 Operation (High Speed Mode) t2 20 20 ns (min) CONVST Pulsewidth t3 25 25 ns (min) SCLK High Pulsewidth t4 25 25 ns (min) SCLK Low Pulsewidth t 3 5 5 5 ns (min) CONVST Rising Edge to SCLK Rising Edge Set-Up Time t 3 6 10 10 ns (max) SCLK Rising Edge to DOUT Data Valid Delay t 3 7 5 5 ns (max) Data Hold Time after Rising Edge SCLK t 3, 4 8 20 20 ns (max) Bus Relinquish Time after Falling Edge of SCLK 10 10 ns (min) tPOWER UP 1.5 1.5 µs (max) Power-Up Time after Rising Edge of CONVST NOTES 1Sample tested to ensure compliance. 2See Figures 14, 15 and 16. 3These numbers are measured with the load circuit of Figure 1. They are defined as the time required for the o/p to cross 0.8 V or 2.4 V for V DD = 5 V ± 10% and 0.4 V or 2 V for VDD = 3 V ± 10%. 4Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t8, quoted in the Timing Characteristics is the true bus relinquish time of the part and as such is independent of external bus loading capacitances. Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*
SOIC Package, Power Dissipation . 450 mW (TA = 25°C unless otherwise noted) θJA Thermal Impedance . 160°C/W VDD to GND . –0.3 V to +7 V θJC Thermal Impedance . 56°C/W Digital Input Voltage to GND Lead Temperature, Soldering (CONVST, SCLK) . –0.3 V, VDD + 0.3 V Vapor Phase (60 sec) . 215°C Digital Output Voltage to GND Infrared (15 sec) . 220°C (DOUT) . –0.3 V, VDD + 0.3 V MicroSOIC Package, Power Dissipation . 450 mW VREF to GND . –0.3 V, VDD + 0.3 V θJA Thermal Impedance . 206°C/W Analog Inputs θJC Thermal Impedance . 44°C/W (VIN+, VIN–) . –0.3 V, VDD + 0.3 V Lead Temperature, Soldering Storage Temperature Range . –65°C to +150°C Vapor Phase (60 sec) . 215°C Junction Temperature . 150°C Infrared (15 sec) . 220°C Plastic DIP Package, Power Dissipation . 450 mW *Stresses above those listed under Absolute Maximum Ratings may cause perma- θJA Thermal Impedance . 125°C/W nent damage to the device. This is a stress rating only; functional operation of the θJC Thermal Impedance . 50°C/W device at these or any other conditions above those listed in the operational Lead Temperature Soldering (10 sec) . 260°C sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ORDERING GUIDE Linearity Temperature Package Package Branding Model Error (LSB) Range Description Options Information
AD7810YN ±1 LSB –40°C to +105°C Plastic DIP N-8 AD7810YR ±1 LSB –40°C to +105°C Small Outline IC (SOIC) SO-8 AD7810YRM ±1 LSB –40°C to +105°C microSOIC RM-8 C1Y
IOL 200
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A TO OUTPUT 1.6V PIN CL 50pF IOH 200
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A
Figure 1. Load Circuit for Digital Output Timing Specifications REV. B –3–