Datasheet AD7722 (Analog Devices) - 8

AD7722 DOE t t 1 5 1 6 SDO
Figure 5. Serial Mode Timing for Data Output Enable and Serial Data Output (TSI = Logic Low)
t17 t18 DRDY t19 t25 CS t20 t24 t21 RD t t23 2 2 DB0–DB15 VALID DATA
Figure 6. Parallel Mode Read Timing
t30 CLKIN t28 MIN t28 MAX t31 SYNC, RESET t26 t27 DVAL t29 DRDY
Figure 7. SYNC and RESET Timing, Serial and Parallel Mode
t36 CLKIN t34 SYNC, RESET t35 t37 UNI = 1 t37 UNI = 0 8192 t DVAL CLK 8192 tCLK 8192 tCLK 8192 tCLK 512 t 512 t 512 t CLK CLK CLK t38 DRDY
Figure 8. Calibration Timing, Serial and Parallel Mode REV. B –7– Document Outline FEATURES FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ORDERING GUIDE TIMING SPECIFICATIONS PIN FUNCTION DESCRIPTIONS PIN CONFIGURATION PARALLEL MODE PIN FUNCTION DESCRIPTIONS SERIAL MODE PIN FUNCTION DESCRIPTIONS TERMINOLOGY Signal-to-Noise Plus Distortion Ratio (S/(N+D)) Total Harmonic Distortion (THD) Spurious-Free Dynamic Range (SFDR) Intermodulation Distortion Pass-Band Ripple Pass-Band Frequency Cutoff Frequency Stop-Band Frequency Stop-Band Attenuation Integral Nonlinearity Differential Nonlinearity Common-Mode Rejection Ratio Unipolar Offset Error Bipolar Offset Error Gain Error Typical Performance Characteristics CIRCUIT DESCRIPTION APPLYING THE AD7722 Analog Input Range Differential Inputs Applying the Reference Input Circuits Clock Generation Varying the Master Clock SYSTEM SYNCHRONIZATION AND CONTROL SYNC Input DVAL Reset Input Power-On Reset Offset and Gain Calibration DATA INTERFACING Parallel Interface SERIAL INTERFACE 2-Channel Multiplexed Operation Serial Interfacing to DSPs OUTLINE DIMENSIONS Revision History