AD7858/AD7858LTYPICAL TIMING DIAGRAMS Figures 2 and 3 show typical read and write timing diagrams for 1.6mAIOL serial Interface Mode 2. The reading and writing occurs after conversion in Figure 2, and during conversion in Figure 3. To TOOUTPUT+2.1V attain the maximum sample rate of 100 kHz (AD7858L) or PINCL 200 kHz (AD7858), reading and writing must be performed 100pF during conversion as in Figure 3. At least 400 ns acquisition 200 AIOH time must be allowed (the time from the falling edge of BUSY to the next rising edge of CONVST) before the next conversion Figure 1. Load Circuit for Digital Output Timing begins to ensure that the part is settled to the 12-bit level. If the Specifications user does not want to provide the CONVST signal, the conver- sion can be initiated in software by writing to the control register. tCONVERT = 4.6 s MAX, 10 s MAX FOR L VERSIONt1 = 100ns MIN, t4 = 50/90ns MAX 5V/3V, t7 = 40/60ns MIN 5V/3Vt1CONVST (I/P)tCONVERTt2BUSY (O/P)SYNC (I/P)t3tt91115616SCLK (I/P)t4t10tt126t6THREE-STATETHREE-DOUT (O/P)DB15DB11DB0STATEt8t7DIN (I/P)DB15DB11DB0 Figure 2. AD7858/AD7858L Timing Diagram for Interface Mode 2 (Reading/Writing After Conversion) tCONVERT = 4.6 s MAX, 10 s MAX FOR L VERSIONt1 = 100ns MIN, t4 = 50/90ns MAX 5V/3V, t7 = 40/60ns MIN 5V/3Vt1CONVST (I/P)tCONVERTt2BUSY (O/P)SYNC (I/P)t3tt91115616SCLK (I/P)t4t10tt126t6THREE-STATETHREE-DOUT (O/P)DB15DB11DB0STATEt8t7DIN (I/P)DB15DB11DB0 Figure 3. AD7858/AD7858L Timing Diagram for Interface Mode 2 (Reading/Writing During Conversion) REV. B –5–
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